LPC55S69 CoreMark, active dual core

naga — Mon, 15 Jul 2019 06:31:22 GMT

Hi,

In the document LPC55S6x Product data sheet Rev 1.1 in chapters:
10.2 CoreMark data
10.3 Power consumption

the performance of the microcontroller at the 12, 48 and 96 MHz frequencies is given under the conditions:
CPU0 active mode
CPU1 sleep mode

What are these performances in terms of both CPU0 and CPU1 being in active mode?

I'm especially interested in computing performance.

It can be considered that master / slave codes are in Flash / Flash, Flash / SRAMX or SRAMX / SRAMX.

Neculai

Re: LPC55S69 CoreMark, active dual core

ZhangJennie — Tue, 16 Jul 2019 04:08:15 GMT

Hi Neculai Agavriloaie

For the moment we only have cormark data when CPU0 in active mode, CPU1 in sleep mode. Other data are to be defined. I will escalate it as a feature request to the related team. but so far we don't have it yet,

Have a great day,
Jun Zhang

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LPC55S69 CoreMark, active dual core

Re: LPC55S69 CoreMark, active dual core