LPC MicrocontrollersのトピックRe: LPC43xx SDRAM EMC D/DQM signal ordering

LPC43xx SDRAM EMC D/DQM signal ordering

leecoakley — Tue, 27 Aug 2019 10:57:51 GMT

I'm working on an LPC4357 based design which uses the EMC with 32-bit SDRAM. BGA256 package.

According to the EMC documentation the controller always accesses the SDRAM in bursts of four words. This means that the ordering of the data signals and byte enables does not matter, and the D0-D31 and DQM0-3 signals can be routed in any order within their respective groups without affecting the operation of the external memory. Is this correct?

I would love to know because it would make my task of routing the SDRAM drastically simpler. I'm pretty sure this will work but I would like some confirmation by more experienced people here.

To spell it out, this means connecting the SDRAM to the EMC like this:

D0 - D13

D1 - D27

D2 - D5

DQM0 - DQM3

DQM1 - DQM2

(etc)

Re: LPC43xx SDRAM EMC D/DQM signal ordering

FelipeGarcia — Tue, 27 Aug 2019 17:19:59 GMT

Hello Lee,

Please check the following application note on chapter 2.3. Here it is explained how to connect EMC to single x32 SDRAM.

https://www.nxp.com/docs/en/application-note/AN11508.pdf

I hope it helps!

Best regards,

Felipe

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Re: LPC43xx SDRAM EMC D/DQM signal ordering

leecoakley — Wed, 28 Aug 2019 09:23:50 GMT

Hi Felipe, I have read that application note before but it doesn't cover this particular aspect of using the EMC. That covers signal integrity issues and multiple memory ICs, but not permissible data pin mappings.

As a general rule when routing memories, you can route any of the bits inside a byte lane in any order. But this EMC controller seems to be a special case where all the data signals can be routed in any order because it only does 32-bit accesses to the memory and never individual bytes. This is what I want to confirm.

Re: LPC43xx SDRAM EMC D/DQM signal ordering

FelipeGarcia — Tue, 03 Sep 2019 15:56:30 GMT

Hi Lee,

Let me ask this internally. I will reply as soon as I receive any feedback.

Best regards,

Felipe

Re: LPC43xx SDRAM EMC D/DQM signal ordering

leecoakley — Mon, 09 Sep 2019 11:57:04 GMT

Thanks Felipe. I will wait before sending the design for assembly. It really did help greatly with the routing, so I hope this trick works...

Re: LPC43xx SDRAM EMC D/DQM signal ordering

FelipeGarcia — Thu, 12 Sep 2019 23:03:09 GMT

Hello Lee,

Please check the below feedback from internal team:

1. The D0-D31 and DQM0-3 signals need to be connected with certain order. These signals will affect the bit order of data which have been read or written. And these signals focus on each word to operate.
2. According to the EMC documentation the controller always accesses the SDRAM in bursts of four words. this means: to be used with the EMC, the SDRAM must be configured for a 128-bit sequential burst .
As long as the address first word address was given by processor, then SDRAM will add the address in the following three words internally. thus 128-bit data can be operated by sequential burst mode.
for example:
For a single 16-bit external SDRAM chip set the burst length to 8. For a single 32-bit SDRAM chip set the burst length to 4.
3.there is a AN11508 in the NXP website which explains the details about SDRAM interface to LPC18xx/43xx EMC.
it also explains the suggested signal connected method.

Hope it helps!

Best regards,
Felipe

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