topic LPC4357: how to setting M4 core frequency at most 204MHz? in LPC Microcontrollers

LPC4357: how to setting M4 core frequency at most 204MHz?

astrogreco — Wed, 06 Mar 2019 12:03:31 GMT

I'm trying to implement PLL1 to set the main clock frequency for the M4 core at most 204MHz.
To set the PLL1 with the PLL1_CTRL register there are no problems. I perform the following instructions:
1) Set AUTOBLOCK
2) Set M and N
3) wait LOCK
4) Set DIRECT
5) wait LOCK
6) clear BYPASS
7) wait LOCK

Each setting is set and the LOCK in PLL1_STAT is always 0.
Unfortunately, when I finally select the CLK_SEL of BASE_M4_CLK at 0x9, the next instruction is no longer executed.
Even if I do this last setting before setting up the PLL1, it does the same problem.

What could be the reason?

Re: LPC4357: how to setting M4 core frequency at most 204MHz?

bernhardfink — Wed, 06 Mar 2019 12:57:12 GMT

A few reasons for this:

You execute from internal flash and after switching to 204MHz the waitstate setting do no longer fit. So set the wait states to the maximum first and then switch to higher frequency.
Other components connected to this PLL output might cause a crash if they are not prepared for this step
You execute from external QSPI flash and the interface speed does no longer match the specifcation when switching to 204MHz
Power supply problems due to the higher power demand at 204MHz (in case it's your own board development)

Regards,

Bernhard.

Re: LPC4357: how to setting M4 core frequency at most 204MHz?

astrogreco — Thu, 07 Mar 2019 16:03:18 GMT

Thanks for the reply. I set the PLL as the first operation.
I solved, the problem was that the PLL1 was not enabled, ie bit 0 (PD) was not clear.
However now it works but I have to skip the wait LOCK phases. In fact, the LOCK bit of PLL1_STAT is never set to 1.
I set the PLL1_CTRL register in several steps, but when I check the LOCK it is always 0.
If I skip the LOCK check the process goes on all the same and everything works.

Attached the function I use.

What could be the problem of LOCK bit?

Re: LPC4357: how to setting M4 core frequency at most 204MHz?

bernhardfink — Thu, 07 Mar 2019 17:01:42 GMT

I must admit that I'm a little bit out of business for this LPC4300 platform, but after a short look into your code I have the follwing recommendations:

If you use a variable to poll for a status which changes with an event from the outside, then declare your variable with the keyword volatile. Otherwise the compiler could do some ugly optimization.
Don't poll on register flags (like the lock bit) in a while loop. At least add some NOP() in the while loop.
If it is recommended to wait after a specific setting, then do it with a simple wait() function. For safety reasons you can then read the lock bit to confirm that it is set.

Regards,

Bernhard.

Re: LPC4357: how to setting M4 core frequency at most 204MHz?

astrogreco — Fri, 08 Mar 2019 14:19:38 GMT

Thank you very much. I solved the problem. NOP operations are required. Now after every PLL1 setting the LOCK bit is set to 1 and the process goes on correctly.

Attached the function used