<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic A possible defect of Chip_ADC_SetClockRate() in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/A-possible-defect-of-Chip-ADC-SetClockRate/m-p/871683#M34756</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm writing to report possible defect of&amp;nbsp;Chip_ADC_SetClockRate() in the LPCOpen 3.03. The content of this function is as below:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; Chip_ADC_SetDivider(pADC, ((Chip_Clock_GetSystemClockRate() + (rate&amp;gt;&amp;gt;2)) / rate) -1);&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It could mistakenly set up the wrong divider to 0xff when the result of&amp;nbsp;&lt;SPAN&gt;((Chip_Clock_GetSystemClockRate() + (rate&amp;gt;&amp;gt;2)) / rate) is zero. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;In case internal XTAL is used (clock-rate is 12MHz) instead of external clock-rate, the adc demo-code of Init_ADC() will call Chip_ADC_SetClockRate(LPC_ADC, ADC_MAX_CLOCK_RATE), in which ADC_MAX_CLOCK_RATE is 50MHz. This will make result of "((Chip_Clock_GetSystemClockRate() + (rate&amp;gt;&amp;gt;2)) / rate)" as 0. Thus after minus 1 the Divider will be set to 0xff.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;It is recommended&amp;nbsp;that some protection or warning is added within&amp;nbsp;Chip_ADC_SetClockRate().&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Jeremy&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 14 Jan 2019 05:33:28 GMT</pubDate>
    <dc:creator>jeremyhsiao</dc:creator>
    <dc:date>2019-01-14T05:33:28Z</dc:date>
    <item>
      <title>A possible defect of Chip_ADC_SetClockRate()</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/A-possible-defect-of-Chip-ADC-SetClockRate/m-p/871683#M34756</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm writing to report possible defect of&amp;nbsp;Chip_ADC_SetClockRate() in the LPCOpen 3.03. The content of this function is as below:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; Chip_ADC_SetDivider(pADC, ((Chip_Clock_GetSystemClockRate() + (rate&amp;gt;&amp;gt;2)) / rate) -1);&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It could mistakenly set up the wrong divider to 0xff when the result of&amp;nbsp;&lt;SPAN&gt;((Chip_Clock_GetSystemClockRate() + (rate&amp;gt;&amp;gt;2)) / rate) is zero. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;In case internal XTAL is used (clock-rate is 12MHz) instead of external clock-rate, the adc demo-code of Init_ADC() will call Chip_ADC_SetClockRate(LPC_ADC, ADC_MAX_CLOCK_RATE), in which ADC_MAX_CLOCK_RATE is 50MHz. This will make result of "((Chip_Clock_GetSystemClockRate() + (rate&amp;gt;&amp;gt;2)) / rate)" as 0. Thus after minus 1 the Divider will be set to 0xff.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;It is recommended&amp;nbsp;that some protection or warning is added within&amp;nbsp;Chip_ADC_SetClockRate().&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Jeremy&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 14 Jan 2019 05:33:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/A-possible-defect-of-Chip-ADC-SetClockRate/m-p/871683#M34756</guid>
      <dc:creator>jeremyhsiao</dc:creator>
      <dc:date>2019-01-14T05:33:28Z</dc:date>
    </item>
    <item>
      <title>Re: A possible defect of Chip_ADC_SetClockRate()</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/A-possible-defect-of-Chip-ADC-SetClockRate/m-p/871684#M34757</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;SPAN&gt;Jeremy&lt;/SPAN&gt;,&lt;/P&gt;&lt;P&gt;Thanks for your sharing, could you please tell me the device you are using, I will check it .&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Alice&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 15 Jan 2019 03:19:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/A-possible-defect-of-Chip-ADC-SetClockRate/m-p/871684#M34757</guid>
      <dc:creator>Alice_Yang</dc:creator>
      <dc:date>2019-01-15T03:19:55Z</dc:date>
    </item>
    <item>
      <title>Re: A possible defect of Chip_ADC_SetClockRate()</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/A-possible-defect-of-Chip-ADC-SetClockRate/m-p/871685#M34758</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Alice,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm using LPC11U66JBD48 and working on my own board without using external XTAL.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Jeremy&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 15 Jan 2019 03:49:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/A-possible-defect-of-Chip-ADC-SetClockRate/m-p/871685#M34758</guid>
      <dc:creator>jeremyhsiao</dc:creator>
      <dc:date>2019-01-15T03:49:45Z</dc:date>
    </item>
    <item>
      <title>Re: A possible defect of Chip_ADC_SetClockRate()</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/A-possible-defect-of-Chip-ADC-SetClockRate/m-p/871686#M34759</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;OK, thanks for your recommendation, I have reported it to development team.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Alice&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 15 Jan 2019 09:46:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/A-possible-defect-of-Chip-ADC-SetClockRate/m-p/871686#M34759</guid>
      <dc:creator>Alice_Yang</dc:creator>
      <dc:date>2019-01-15T09:46:19Z</dc:date>
    </item>
  </channel>
</rss>

