topic Re: IPC Implementation issue with all three Cores in LPC4367 (M4,M0Sub and M0App) in LPC Microcontrollers

IPC Implementation issue with all three Cores in LPC4367 (M4,M0Sub and M0App)

gauravmore — Mon, 07 Jan 2019 06:38:03 GMT

Hi,

I am using LPC4367 for the first time in one of the project. I want to use the IPC mechanism for sharing and tranfering the data between the cores. There are three cores in LPC4367 (M4, M0Sub, M0App). I have implemented IPC mechanism to send the data from M0Sub to M4 , M4 to M0Sub and From M0App to M4 and M4 to M0App. I am using IPC queue mechanism as suggested in the UM10503 manual.

I am transfering the data from M0Sub and M4 at every 625uS and i have checked it is working fine when data is transfered from M0Sub to M4.

I am tranfersing data from M0App to M4 and M4 is responding to M0App after recieving the query from M0App. But here after some time means immediately the Status = IPC_tryPushMsg(g_st_msgRx.cpuid,&g_st_msgRx); is QUEUE_FULL. I am unable to find the issue since this is working fine with M0Sub and M4.

Aso request you to please provide the sample code or source code for IPC mechanism implementation using three cores using IPC queue mechnism .Here i am using the Inerrupt mechanism of the queue.

One more thing is that i am using same address location for trigering the M4 M0App and M0Sub (0x20000000) As specified in UM10503 Manual.

#define SHARED_MEM_IPC_ 0x20000000

static struct ipc_queue *q_ipc = (struct ipc_queue *) SHARED_MEM_IPC_;

Request you to please provide the solution for the same since it is on very high prioroty.

I refered M4-M0 core synchronisation / lock mechanism using mutex or semaphore since it the same issue but lititle different since it is related to RTOS.

Thanks

Gaurav More

Re: IPC Implementation issue with all three Cores in LPC4367 (M4,M0Sub and M0App)

bernhardfink — Mon, 07 Jan 2019 10:13:07 GMT

Hi Gaurav,

there is a difference in the bus connection between the M0App and the M0Sub.

The M0App is a bus master and has the same rights and timings as the M4
The M0Sub is a peripheral core behind a bus sychronisation bridge, every transfer to/from this core (and to the dedicated SRAM memory section) happens with 4 waitstates. However, the core itself on its dedicated SRAM section works without waitstates.

Maybe that's "somehow" the reason for this overflow.

Regards,

Bernhard.

Re: IPC Implementation issue with all three Cores in LPC4367 (M4,M0Sub and M0App)

soledad — Mon, 07 Jan 2019 18:26:42 GMT

Hi,

In addition I suggest to check the application note AN11177 Inter Processor Communication,

AN11177: Inter Processor Communications.

this appnote provides information about:

The API implementation for dual core communication on LPC43xx targets.
How to include or exclude functionality by means of a platform-wise configuration file.
System level settings and debug options to be aware of when changing the configuration.

Have a great day,
Sol

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