LPC MicrocontrollersのトピックRe: LPC1830 ADC specs

LPC1830 ADC specs

yoshiyukiokada — Fri, 07 Dec 2018 09:36:08 GMT

Hi community team,

I'm checking an ADC specs of LPC1830 and I have some questions as blew;

1. What is a Ri? The Ri is not shown in "Fig 40. ADC interface to pins" of datasheet.

2. What is the relationship between Rvsi and Ri?

3. What was a calculation process of "Rvsi = 1/(7 x fclk(adc) x Cia)"?

4. Are there any documents which explain a detailed block diagram of ADC.

Best regards,

Yoshi

Re: LPC1830 ADC specs

xiangjun_rong — Mon, 10 Dec 2018 06:57:37 GMT

Hi, Okada,

I suggest you can refer to section 3.1 Input Impedance in an1974.pdf, although it talks about DSC, I think is applies for the ADC of LPC family, because the ADC mechanism is the same.

Hope it can help you

XiangJun Rong

Re: LPC1830 ADC specs

yoshiyukiokada — Tue, 11 Dec 2018 14:23:27 GMT

Hi XiangJun,

Thank you for your help. I read the section 3.1 and 3.2 of AN1974 however it is still unclear.

Would you mind to answer to my questions as below;

1. What is a Ri? The Ri is not shown in "Fig 40. ADC interface to pins" of datasheet.

Ri is calculated with ADC clock rate in AN1974. On the other hand, Ri is calculated with sampling frequency in LPC1830 data sheet. Is the Ri in AN1974 same to Ri in LPC1830 data sheet?

2. What is the relationship between Rvsi and Ri?

3. What was a calculation process of "Rvsi = 1/(7 x fclk(adc) x Cia)"?

Best regards

Yoshi

Re: LPC1830 ADC specs

xiangjun_rong — Wed, 12 Dec 2018 08:32:13 GMT

Hi, Okada,

As you know that the ADC converter has a SAMPLE/HOLD capacitor called Cia in the data sheet of LPC1830, there are two stage for the SAMPLE/HOLD circuit, the first stage is sampling stage, in the stage, the external input source charges the Cia capacitor, assume we charge the cap with a voltage source, the voltage source voltage is Vsample, the current is assumed as Isample, we can get a resistor by Vsample/Isample, the resistor is Rvsi. After the charging stage is over, the cap has been charged to a voltage which is equals to the external voltage source, the sampling switch is turned off, the cap will HOLD the voltage, the ADC will convert the voltage, at the time, the resistor is Ri.

So the Rvsi is more important than the Ri.

In conclusion, you have to meet the requirement of the Rs value as Fig 40, Rs is the external tested voltage output impedance, so if your external tested voltage output impedance is larger than the calculated Rs, an analog buffer based on OP AMP is required.

This is only my opinion, hope it can help you.

Re: LPC1830 ADC specs

yoshiyukiokada — Fri, 14 Dec 2018 02:13:46 GMT

Hi Xiangjun,

Thank you for your explanation. I'm starting to understand. In order to deepen my understanding, let me make sure two more things.

1. Rvsi = 1/(7 x fclk(adc) x Cia). In this equation, what is the '7' ? I referred AN1974, however, there was no information about coefficient.

2. In the LPC1830 datasheet, max value of Ri is defined as 1.2 Mohm. And, Ri is also calculated using following formula. Cia is upto 2pF and fs is upto 400K/samples. With these condition, Ri is about 1.25 Mohm. I think that the value "1.2 Mohm" is not max value but min value because Ri is inversely proportional to fs. Is my understanding correct?

Best regards,

Yoshi

Re: LPC1830 ADC specs

xiangjun_rong — Tue, 08 Jan 2019 02:42:25 GMT

Hi, Yoshi,

This is the design team reply, I copy the reply here:

Xiangjun Rong

Rvsi is related to the output resistance of the voltage source (Rs) during the ADC0/1. This mean Rs should be < Rvsi.

Ri is the input resistance that appears across the Rs, which will contribute to the accuracy of the ADC measurement.

As an example, you have a resistor divider to get 30V down to 3V at ADC input, using R1 = 18k and R2 = 2k ohm

This mean Rs = 1.8k ohmn (R1 in parallel with R2).

The input resistance (1.2MΩ) appears in parallel with your lower divider resistor (2k ohm) so it will appear as 1.9967kΩ, giving a worst-case error of 0.165%.

Assuming that you are using 1% tolerance resistors, then the error from the input resistance of the A/D converter will be less than the error contribution from the resistor tolerance; and probably better than the tolerance on your reference voltage (VDDA), which is your 3.3V supply voltage.

Re: LPC1830 ADC specs

yoshiyukiokada — Tue, 08 Jan 2019 12:54:42 GMT

Hi XiangJun,

I understood the relationship between Ri and Rvsi. Thank you for your support.

Could you please continue to check the remaining questions as below;

1. Rvsi = 1/(7 x fclk(adc) x Cia). In this equation, what is the '7' ? I referred AN1974, however, there was no information about coefficient.

Best regards,

Yoshi

Re: LPC1830 ADC specs

xiangjun_rong — Tue, 29 Jan 2019 08:43:12 GMT

Hi, Yoshi,

sorry for the delay.

This is the reply from Design team:

The '7' is related to the time constant required for an RC circuit to settle. It means the time should be sufficient to ensure the Cia is charged enough.

The 1.2Mohm is the max not min. The 400ksamples/s is the min which can be configured. The fs can only be set to the bigger with the resolution being set to the lower.

Xiangjun Rong

Re: LPC1830 ADC specs

yoshiyukiokada — Wed, 30 Jan 2019 12:03:58 GMT

Hi XiangJun,

Thank you for your help.

>The 400ksamples/s is the min which can be configured.

According to the datasheet, the sampling frequency is upto 400k samples/s when an accuracy is 10 bit resolution.

That means the 400k samples/s is only available sampling frequency for 10 bit resolution.

Is my understanding correct?

Best regards,

Yoshi

Re: LPC1830 ADC specs

xiangjun_rong — Thu, 31 Jan 2019 07:22:51 GMT

Hi, Yoshi,

I think You are right that "According to the datasheet, the sampling frequency is upto 400k samples/s when an accuracy is 10 bit resolution", in other words, in the 10 bits resolution, the ADC maximum sampling frequency is 400KHz.

For the line "

based on the above formula and 400KHz maximum sampling frequency and 2pF capacitor, so I agree with you that 1.2Mohm Ri is the minimum value rather than maximum only at the condition 10 bits resolution.

If user uses less bits resolution, the sampling frequency will be higher, the Ri will be less. The design team considers the less ADC resolution condition.

Hope it can help you

XiangJun Rong

Re: LPC1830 ADC specs

yoshiyukiokada — Thu, 31 Jan 2019 10:16:56 GMT

Hi XiangJun,

Thank you for your help.

I understood this topic very well.

Best regards,

Yoshi.

Re: LPC1830 ADC specs

rayliao — Fri, 10 Apr 2020 08:59:36 GMT

Hi XiangJun,

According to the Ri formula and your comment,

I think the sampling frequency only could be bigger than 400k samples/s, but sample code shows it could be changed under 400K samples/s

else if (bufferUART == 'o') {
_bitRate -= _bitRate > 0 ? 1000 : 0;
Chip_ADC_SetSampleRate(_LPC_ADC_ID, &ADCSetup, _bitRate);
DEBUGOUT("Rate : %d Sample/s - Accuracy : %d bit \r\n", _bitRate, 10 - _bitAccuracy);
}
else if (bufferUART == 'p') {
_bitRate += _bitRate < 400000 ? 1000 : 0;
Chip_ADC_SetSampleRate(_LPC_ADC_ID, &ADCSetup, _bitRate);
DEBUGOUT("Rate : %d Sample/s - Accuracy : %d bit \r\n", _bitRate, 10 - _bitAccuracy);

BR,

Ray