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    <title>LPC Microcontrollers中的主题 How To make a plain load image with M0 cores</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/How-To-make-a-plain-load-image-with-M0-cores/m-p/820467#M32828</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;LPC43S70 can load AES encrypted image from QSPI flash using SPIFI.&lt;/P&gt;&lt;P&gt;The problem is, images of M0 cores cannot be copied to right position so that M0 cores cannot boot up correctly, while the M4 core works just fine.&lt;/P&gt;&lt;P&gt;plus, Normal image(XIP in QSPI flash) can boot up correctly.&lt;/P&gt;&lt;P&gt;Help wanted.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Memory map:&lt;/P&gt;&lt;P&gt;M4: use Plain Load Image option, addr: 0x1000_0000&lt;/P&gt;&lt;P&gt;M0APP addr: 0x2000_0000&lt;/P&gt;&lt;P&gt;M0SUB addr: 0x1800_0000&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sun, 02 Dec 2018 08:07:32 GMT</pubDate>
    <dc:creator>zhengyangqu</dc:creator>
    <dc:date>2018-12-02T08:07:32Z</dc:date>
    <item>
      <title>How To make a plain load image with M0 cores</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/How-To-make-a-plain-load-image-with-M0-cores/m-p/820467#M32828</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;LPC43S70 can load AES encrypted image from QSPI flash using SPIFI.&lt;/P&gt;&lt;P&gt;The problem is, images of M0 cores cannot be copied to right position so that M0 cores cannot boot up correctly, while the M4 core works just fine.&lt;/P&gt;&lt;P&gt;plus, Normal image(XIP in QSPI flash) can boot up correctly.&lt;/P&gt;&lt;P&gt;Help wanted.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Memory map:&lt;/P&gt;&lt;P&gt;M4: use Plain Load Image option, addr: 0x1000_0000&lt;/P&gt;&lt;P&gt;M0APP addr: 0x2000_0000&lt;/P&gt;&lt;P&gt;M0SUB addr: 0x1800_0000&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 02 Dec 2018 08:07:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/How-To-make-a-plain-load-image-with-M0-cores/m-p/820467#M32828</guid>
      <dc:creator>zhengyangqu</dc:creator>
      <dc:date>2018-12-02T08:07:32Z</dc:date>
    </item>
    <item>
      <title>Re: How To make a plain load image with M0 cores</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/How-To-make-a-plain-load-image-with-M0-cores/m-p/820468#M32829</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A _jive_internal="true" data-content-finding="Community" data-userid="316036" data-username="zhengyangqu" href="https://community.nxp.com/people/zhengyangqu"&gt;Zhengyang Qu&lt;/A&gt;,&lt;/P&gt;&lt;P&gt;Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.&lt;BR /&gt;I'd highly recommend you to directly debug the dual-core demo in the RAM as the first step to the implementing the secure boot, as it can give you some clues about the 'issue', please give a try.&lt;BR /&gt;Have a great day,&lt;BR /&gt;TIC&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 06 Dec 2018 02:46:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/How-To-make-a-plain-load-image-with-M0-cores/m-p/820468#M32829</guid>
      <dc:creator>jeremyzhou</dc:creator>
      <dc:date>2018-12-06T02:46:27Z</dc:date>
    </item>
    <item>
      <title>Re: How To make a plain load image with M0 cores</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/How-To-make-a-plain-load-image-with-M0-cores/m-p/820469#M32830</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have already implement boot all of the three cores from spifi flash.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 12 Dec 2018 05:20:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/How-To-make-a-plain-load-image-with-M0-cores/m-p/820469#M32830</guid>
      <dc:creator>zhengyangqu</dc:creator>
      <dc:date>2018-12-12T05:20:59Z</dc:date>
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