LPC MicrocontrollersのトピックRe: LPC18xx: CGU AUTOBLOCK bit

LPC18xx: CGU AUTOBLOCK bit

naoa — Fri, 30 Nov 2018 07:13:50 GMT

Hi,

I've found following updated notes about PLL1 settings in the latest LPC18xx User Manual.
However, our old products did not deal with this.

12.6.5.2 PLL1 control register
Table 123. PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description
:
[1] When the PLL1 is enabled, set the AUTOBLOCK bit in the PLL1_CTRL register to 1. This bit
re-synchronizes the clock output during frequency changes that prevents glitches when switching clock
frequencies.

I changed the frequency of PLL 1 as shown below, but will glitch occur?
And, what happens to the CPU when glitch occurs?

Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_IRC, true, false);
Chip_Clock_EnableCrystal();
Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, 12000000, 180000000, 180000000); // note: PLL1 divide by 2
while(!Chip_Clock_MainPLLLocked());
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);

for(int delay=0; delay<= 1240*10; delay++);// Wait 50 us

LPC_CGU->PLL1_CTRL |= (1 << 7) ; /* DIRECT 90MHz -> 180MHz */

Re: LPC18xx: CGU AUTOBLOCK bit

jeremyzhou — Mon, 03 Dec 2018 02:55:55 GMT

Hi 尚久荒川,

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
After having a review of your code, I found that you basically follow the steps which are illustrated in 12.2.1.2 Changing the BASE_M3_CLK after waking up from deep-sleep or power-down modes.
I'd like to if you can introduce the glitch you mentioned and I was wondering if you can share the demo which can replicate this phenomenon.

I'm looking forward to your reply.
Have a great day,
TIC

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

Re: LPC18xx: CGU AUTOBLOCK bit

naoa — Tue, 04 Dec 2018 02:10:20 GMT

Hi jeremyzhou, thank you very much for your fast and accurate reply.

My product is old.
I basically follow the procedure outlined in LPC18xx User manual Rev.2.8, 12.2.1.1 Changing the BASE_M3_CLK after power-up, reset, or deep power-down mode.
And, I am using the legacy version of LPCOpen v2.20.
v2.20 does not set the AUTOBLOCK bit in the Chip_Clock_SetupMainPLLHz function.

I have tested tens of thousands of times, but the problem has not occurred.
Is it unnecessary to set the AUTOBLOCK bit in my product?

Re: LPC18xx: CGU AUTOBLOCK bit

jeremyzhou — Wed, 05 Dec 2018 03:19:19 GMT

Hi 尚久荒川,

Thanks for your reply.
I believe it's unnecessary to set the AUTO BLOCK bit (bit 11) after checking the various versions of LPCOpen library.

Hope this is clear.
Have a great day,
TIC