topic Re: SPIFI interface and LCD controller in LPC1857 in LPC Microcontrollers

SPIFI interface and LCD controller in LPC1857

vinaymanikkoth — Wed, 31 Jan 2018 00:59:43 GMT

Hi,

I need help to understand an issue i am facing while using SPIFI interface & LCD controller.

I took Flexible camera demo from NXP.

would like to make use of the SPIFI interface. so moved the LCD buffer from SDRAM to SPIFI memory. camera buffer still in SDRAM.

Initialized the SPIFI interface to memory mapped from location 0x14000000.

initialized LCD and mapped to the upper panel base address as 0x14000000.

when there is a new frame from camera, did a reset to SPIFI interface to come out of memory mode. after that copied the frame from SDRAM to spifi memory using spifi command register.

at the end, moved the SPIFI interface back to memory mapped mode.

my observation: LCD was reading from spifi memory till i do the first spifi interface reset. after that LCD is not getting updated. am i doing something wrong?

Thanks

Re: SPIFI interface and LCD controller in LPC1857

bernhardfink — Wed, 31 Jan 2018 11:32:05 GMT

Just to make sure that we have the same understanding:

If the LCD buffer is in the QSPI memory area, then this automatically means that it is read-only for the LCD controller
With the ARM you can read from it in memory mapped mode
With the ARM you can (re-)program the QSPI using the API from the SPIFI driver

What you can't do:

Simply write to the QSPI in memory mapped mode
Access the QSPI in memory mapped mode (for example with the LCD controller) during programming

Re: SPIFI interface and LCD controller in LPC1857

vinaymanikkoth — Thu, 01 Feb 2018 23:25:59 GMT

If the LCD buffer is in the QSPI memory area, then this automatically means that it is read-only for the LCD controller

Yes, I am treating this as a read only memory. Can I update the memory by changing from memory mode to command mode and turn on the memory mode after the update?

After enabling memory mode, updating the upbase or lpbase address of the lcd controller will initiate a interrupt to update the display image. Am I correct?

Re: SPIFI interface and LCD controller in LPC1857

bernhardfink — Fri, 02 Feb 2018 10:09:15 GMT

When you say "update the memory", then this means "Write". So you don't treat it as RO memory.

A TFT is updated all the time, let's say 30 times per second. If you don't stop the LCD controller before you set the QSPI to programming mode, the LCD controller DMA will try to access a memory which is in fact not accessible.

When you have more than one display frame stored in the QSPI, then you can switch at any point in time the basepointer to the new frame start address, you don't need to stop the LCD controller for this.

Re: SPIFI interface and LCD controller in LPC1857

vinaymanikkoth — Sat, 10 Feb 2018 23:56:04 GMT

so if i am using SPIFI as display buffer, have to do a 150KB read (240x320 display) in 6ms. Can i do it?

why there is a idle time (no spi/qpi clock for some time) after every 32bit access?

Re: SPIFI interface and LCD controller in LPC1857

bernhardfink — Mon, 12 Feb 2018 12:33:51 GMT

If I use a calculator and use these values: f(spifi) = 6ms / (150000 *2)

then you see, that at 50MHz you would get a raw rate of 150kbyte per 6ms. Taking breaks into account means, that you should maybe work with 72MHz or higher. Let's go for 90MHz, because this is 180MHz / 2.

Breaks in communications on memory bus systems are either there by design or because of other bus masters with a currently higher priority are allocating the bus. So the the overall system load might influence the performance of the SPIFI interface.