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    <title>LPC MicrocontrollersのトピックRe: Failed to connect to CPU</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Failed-to-connect-to-CPU/m-p/751452#M30246</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Thanapon,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It seems that you need to&amp;nbsp;recover debug access to the MCU. Please refer to the following community post:&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/389112"&gt;Regaining debug access to target MCU&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope it helps!&lt;/P&gt;&lt;P&gt;Victor.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 16 May 2018 20:02:24 GMT</pubDate>
    <dc:creator>victorjimenez</dc:creator>
    <dc:date>2018-05-16T20:02:24Z</dc:date>
    <item>
      <title>Failed to connect to CPU</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Failed-to-connect-to-CPU/m-p/751451#M30245</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am using LPC1817 and IAR Embedded Workbench 7.70.2.&lt;BR /&gt;and found this log when run download and debug via i-jet/JTAGjet.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;---------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Tue May 15, 2018 09:27:10: IAR Embedded Workbench 7.70.2 (armproc.dll) &lt;BR /&gt;Tue May 15, 2018 09:27:10: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.5\arm\config\debugger\NXP\LPC18xx_LPC43xx.dmac &lt;BR /&gt;Tue May 15, 2018 09:27:10: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.5\arm\config\flashloader\NXP\FlashNXPLPC18xx.mac &lt;BR /&gt;Tue May 15, 2018 09:27:11: Loading the I-jet/JTAGjet driver &lt;BR /&gt;Tue May 15, 2018 09:27:11: Probe: Probe SW module ver 1.56 &lt;BR /&gt;Tue May 15, 2018 09:27:11: Probe: Option: trace(Auto,size_limit=100%) &lt;BR /&gt;Tue May 15, 2018 09:27:11: Probe: I-jet-Trace SW module ver 1.61 &lt;BR /&gt;Tue May 15, 2018 09:27:11: Probe: Found I-jet, SN=82573 &lt;BR /&gt;Tue May 15, 2018 09:27:11: Probe: Opened connection to I-jet:82573 &lt;BR /&gt;Tue May 15, 2018 09:27:11: Probe: USB connection verified (11712 packets/sec) &lt;BR /&gt;Tue May 15, 2018 09:27:11: Probe: I-jet, FW ver 4.2, HW Ver:A &lt;BR /&gt;Tue May 15, 2018 09:27:11: Probe: IJET-ARM20 adapter detected &lt;BR /&gt;Tue May 15, 2018 09:27:11: Probe: Versions: JTAG=1.76 SWO=1.36 A2D=1.70 Stream=1.47 SigCom=2.41 &lt;BR /&gt;Tue May 15, 2018 09:27:11: EARM v.4.4 &lt;BR /&gt;Tue May 15, 2018 09:27:11: Emulation layer version 4.4 &lt;BR /&gt;Tue May 15, 2018 09:27:11: JTAG clock detected: 12MHz &lt;BR /&gt;Tue May 15, 2018 09:27:11: Chain detected: 1 device, total IR length 4. &lt;BR /&gt;Tue May 15, 2018 09:27:11: BoardCfg=!Cortex &lt;BR /&gt;Tue May 15, 2018 09:27:11: Notification to core-connect hookup. &lt;BR /&gt;Tue May 15, 2018 09:27:11: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:11: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o Debugging is not possible. &lt;BR /&gt;&lt;STRONG&gt;Tue May 15, 2018 09:27:11: CPU status FAILED&lt;/STRONG&gt; &lt;BR /&gt;Tue May 15, 2018 09:27:11: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:11: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:11: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:11: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:11: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:11: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:11: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:11: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:11: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:11: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:11: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:11: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:11: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:11: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:11: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:11: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:11: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:12: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:12: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:12: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:12: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:12: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:12: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:12: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:12: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:12: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:12: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:12: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:12: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:12: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:12: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:12: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:12: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:12: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:12: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:12: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:12: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:12: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:12: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:12: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:12: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:12: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:12: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:12: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:12: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:12: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:12: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:12: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:12: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:12: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:13: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:13: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:13: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:14: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:14: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:14: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:14: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:14: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:14: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:14: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:14: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:14: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:14: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:14: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:14: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:14: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:14: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:14: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:14: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:14: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:14: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:14: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:14: LowLevelReset(hardware, delay 200) &lt;BR /&gt;Tue May 15, 2018 09:27:15: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:15: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:15: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:15: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:15: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:15: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:15: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:15: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:15: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:15: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:15: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:15: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:15: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:15: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:15: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:15: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o Debugging is not possible. &lt;BR /&gt;Tue May 15, 2018 09:27:15: CoreSight error: Debug interface power and clock request signal has not been acknowledged: &lt;BR /&gt;Tue May 15, 2018 09:27:15: o CDBGPWRUPACK signal expected in response to assertion of debug power request CDBGPWRUPREQ. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o DAP DP STAT register is 0xd0000000. &lt;BR /&gt;Tue May 15, 2018 09:27:15: o Debugging is not possible. &lt;BR /&gt;&lt;STRONG&gt;Tue May 15, 2018 09:27:17: Fatal error: Failed to connect to CPU Session aborted!&lt;/STRONG&gt; &lt;BR /&gt;Tue May 15, 2018 09:27:17: Unloaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.5\arm\config\flashloader\NXP\FlashNXPLPC18xx.mac &lt;BR /&gt;Tue May 15, 2018 09:27:17: IAR Embedded Workbench 7.70.2 (armproc.dll) &lt;BR /&gt;Tue May 15, 2018 09:27:18: Loading the I-jet/JTAGjet driver &lt;BR /&gt;---------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;How to solve "Fatal error: Failed to connect to CPU Session aborted!"??&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;BR /&gt;Thanapon&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 15 May 2018 03:12:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Failed-to-connect-to-CPU/m-p/751451#M30245</guid>
      <dc:creator>thanaponjirapan</dc:creator>
      <dc:date>2018-05-15T03:12:54Z</dc:date>
    </item>
    <item>
      <title>Re: Failed to connect to CPU</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Failed-to-connect-to-CPU/m-p/751452#M30246</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Thanapon,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It seems that you need to&amp;nbsp;recover debug access to the MCU. Please refer to the following community post:&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/389112"&gt;Regaining debug access to target MCU&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope it helps!&lt;/P&gt;&lt;P&gt;Victor.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 16 May 2018 20:02:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Failed-to-connect-to-CPU/m-p/751452#M30246</guid>
      <dc:creator>victorjimenez</dc:creator>
      <dc:date>2018-05-16T20:02:24Z</dc:date>
    </item>
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