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    <title>LPC Microcontrollersのトピック LPC4370 TFBGA100 and SDRAM</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4370-TFBGA100-and-SDRAM/m-p/718391#M29021</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm new to all of these. Is it possible to configure an 8-bit SDRAM to a 100TFLBGA LPC4370? Noticed there's only a single address pin BA0 (EMC_A13) on the 100pin package.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 10 Apr 2018 08:04:58 GMT</pubDate>
    <dc:creator>anitsirk</dc:creator>
    <dc:date>2018-04-10T08:04:58Z</dc:date>
    <item>
      <title>LPC4370 TFBGA100 and SDRAM</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4370-TFBGA100-and-SDRAM/m-p/718391#M29021</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm new to all of these. Is it possible to configure an 8-bit SDRAM to a 100TFLBGA LPC4370? Noticed there's only a single address pin BA0 (EMC_A13) on the 100pin package.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Apr 2018 08:04:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4370-TFBGA100-and-SDRAM/m-p/718391#M29021</guid>
      <dc:creator>anitsirk</dc:creator>
      <dc:date>2018-04-10T08:04:58Z</dc:date>
    </item>
    <item>
      <title>Re:  LPC4370 TFBGA100 and SDRAM</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4370-TFBGA100-and-SDRAM/m-p/718392#M29022</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;It's possible to connect an 8-bit SDRAM device, shown in Fig 63 in the User Manual.&lt;/P&gt;&lt;P&gt;As you can't cascade devices to a 16-bit or even 32-bit wide memory, you don't need a second Bank Activate pin, you just have one bank available --&amp;gt; one pin.&lt;/P&gt;&lt;P&gt;There are two chip selects EMC_DYCS[1:0] available, so in fact you could connect two 8-bit SDRAM devices.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Bernhard.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Apr 2018 10:00:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4370-TFBGA100-and-SDRAM/m-p/718392#M29022</guid>
      <dc:creator>bernhardfink</dc:creator>
      <dc:date>2018-04-10T10:00:53Z</dc:date>
    </item>
    <item>
      <title>Re:  LPC4370 TFBGA100 and SDRAM</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4370-TFBGA100-and-SDRAM/m-p/718393#M29023</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you, &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/bernhardfink"&gt;bernhardfink&lt;/A&gt;! That's very helpful. Most of the 8-bit SDRAMs (IS42S83200G) has a DQM pin but I don't see any recommended connection on the LPC4370's user manual and AN11508 Application Note also, EMC-DQMOUT[3:0] are only available on the LBGA256 package. Can I leave this open on the SDRAM side?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Apr 2018 11:45:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4370-TFBGA100-and-SDRAM/m-p/718393#M29023</guid>
      <dc:creator>anitsirk</dc:creator>
      <dc:date>2018-04-11T11:45:06Z</dc:date>
    </item>
    <item>
      <title>Re:  LPC4370 TFBGA100 and SDRAM</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4370-TFBGA100-and-SDRAM/m-p/718394#M29024</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Kristina,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;as there is nothing to mask with an 8-bit data bus, the EMC doesn't need to provide such a signal to the SDRAM.&lt;/P&gt;&lt;P&gt;You can simply keep this input on the SDRAM in active state, which means LOW --&amp;gt; pulldown resistor.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If you want to have it flexible for some reason, you can connect a GPIO of the LPC4300 to this pin as well, together with a pulldown. Then you could control from the MCU side with the GPIO if the values on the data bus pins are ignored (= masked) from the SDRAM or accepted.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Bernhard.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Apr 2018 10:11:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4370-TFBGA100-and-SDRAM/m-p/718394#M29024</guid>
      <dc:creator>bernhardfink</dc:creator>
      <dc:date>2018-04-12T10:11:16Z</dc:date>
    </item>
    <item>
      <title>Re:  LPC4370 TFBGA100 and SDRAM</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4370-TFBGA100-and-SDRAM/m-p/718395#M29025</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you, &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/bernhardfink"&gt;bernhardfink&lt;/A&gt;‌. This answers my question!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 04 Jun 2018 11:07:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4370-TFBGA100-and-SDRAM/m-p/718395#M29025</guid>
      <dc:creator>anitsirk</dc:creator>
      <dc:date>2018-06-04T11:07:23Z</dc:date>
    </item>
    <item>
      <title>Re:  LPC4370 TFBGA100 and SDRAM</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4370-TFBGA100-and-SDRAM/m-p/718396#M29026</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/bernhardfink"&gt;bernhardfink&lt;/A&gt;‌, is there a sample code to access the EMC of the LPC4370? &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 18 Oct 2018 10:51:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4370-TFBGA100-and-SDRAM/m-p/718396#M29026</guid>
      <dc:creator>anitsirk</dc:creator>
      <dc:date>2018-10-18T10:51:56Z</dc:date>
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