topic Re: Dhrystone on LPC4300 series in LPC Microcontrollers

Dhrystone on LPC4300 series

katisr — Thu, 31 Aug 2017 14:17:18 GMT

Hello all,

I am interested in applying benchmarks on LPC43xx series. Recently I found this link: https://community.nxp.com/thread/420583
In this post," Content originally posted in LPCWare by jokn on Thu Jan 03 05:08:31 MST 2013" - in his post, he mentions that dhrystone was made to run 1 million runs. My question is: So, did M4 and M0 runs together here ? I mean, is parallel programming done here? Dhrystone is a benchmark with integer calculations for computer systems. Hence , Is that 1 million run divided between the m0 core and m4 core ? If yes,how was it achieved ? If no, did only m4 work?

Re: Dhrystone on LPC4300 series

soledad — Thu, 07 Sep 2017 19:58:47 GMT

Hi,

Please check the below videos:

NXP LPC4300 - Get the Most Performance Out of Your Cortex-M4|NXP

NXP LPC4300 - When to Choose ARM Cortex-M4 and Why Dual-Core?|NXP

Have a great day,
Soledad

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Re: Dhrystone on LPC4300 series

katisr — Sun, 10 Sep 2017 12:43:09 GMT

Thank you soledad It shows that the dhrystone/coremark both the benchmarks runs in parallel on the individual cores but they do not communicate. For eg: In dhrystone , if there are , 1 million calculations. The number 1 million is not divided for both the cores (M4 and M0 does not take half-million each and calculate),but instead each core runs the 1 million calculation separately on them . The code for m4 and m0 core runs on them separately. Hence the task is not divided for two cores and the results are communicated via IPC. Instead, they both work on same task as their own individual task. The two individual DMIPS are added. Am I right ?