topic Re: LPC8xx USART synchronous master mode SCLK edge in LPC Microcontrollers

LPC8xx USART synchronous master mode SCLK edge

johanmyréen — Mon, 14 Aug 2017 12:31:29 GMT

My question is about the USART module in the LPC8xx series microcontrollers. If the USART is transmitting in synchronous mode, does the signal transition on the rising or falling edge of SCLK, i.e. should the receiver sample it on the falling or rising edge of SCLK? I can't find this information in the User's Guide. The guide mentions CLKPOL (bit 12 in the USART config register), which determines the clock edge used by the receiver. Does this bit also affect the transmitter, or is there some other way to select the edge? If CLKPOL also affects the transmitter, I would assume the signal transition would happen on the opposite edge, so that similarly configured devices could communicate with each other.

Re: LPC8xx USART synchronous master mode SCLK edge

jeremyzhou — Tue, 15 Aug 2017 08:24:06 GMT

Hi Johan Myréen,

Thank you for your interest in NXP Semiconductor products and

for the opportunity to serve you.

1) does the signal transition on the rising or falling edge of SCLK?

A bit will occupy a complete period of SCLK (Fig 1), not transferring on the rising or falling edge of SCLK.

Fig 1

Have a great day,

TIC

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Re: LPC8xx USART synchronous master mode SCLK edge

johanmyréen — Tue, 15 Aug 2017 10:22:56 GMT

Well, to be precise, a bit will not occupy the complete period of SCLK: it is not valid for a period of time around the clock edge when the output changes state (transitions). It is not made clear in the User Manual which edge polarity should be used, but I can see now from the diagram above that a bit should be sampled on the rising edge of SCLK if CLKPOL = 1. The User Manual only mentions "received data" in the description of CLKPOL, maybe the manual should be edited to mention that it also affects how sent data is clocked out?