EEPROM programing and IRQ question

javiervallori — Mon, 02 Oct 2017 08:27:44 GMT

Hi,

we have a product that do a EEPROM programing within the main App. The app runs on a LPC43S67, wich EEPROM operation access works via memory on the AHB bus. Beside the App uses CAN and SCT IRQs.

The user manual of the corresponding chip indicates the following:

"The erase/program cycle is triggered by
writing 0x6 to the CMD register. The page that is programmed is determined by the
address of the last AHB transfer. Therefore it is advised to perform a page write with
the page address and to prevent AHB reads between page register writes and the
erase/program trigger."

My question is, is it recommended to disable the IRQs during the EEPROM programing operation to avoid within the IRQ a AHB transfer and wrongly change the "last AHB transfer address"? Or the "last AHB transfer address" is just referred to EEPROM's address range?

Thank you.

Re: EEPROM programing and IRQ question

Carlos_Mendoza — Thu, 05 Oct 2017 20:39:15 GMT

Hi Javier,

There is no need to disable the interrupts during the EEPROM Write/Erase. I would recommend you to use the periph_eeprom example that comes with LPCOpen as reference for your application:

LPCOpen Software for LPC43XX|NXP

Hope it helps!

Best Regards,
Carlos Mendoza
Technical Support Engineer

topic EEPROM programing and IRQ question in LPC Microcontrollers

EEPROM programing and IRQ question

Re: EEPROM programing and IRQ question