LPC MicrocontrollersのトピックLPC1788 SD card interface MCLK clock

LPC1788 SD card interface MCLK clock

lpcware — Wed, 15 Jun 2016 17:34:18 GMT

Content originally posted in LPCWare by wella-tabor on Thu Aug 20 05:57:03 MST 2015
Hello,

there is in the LPC1788 UM10470-SD card interface mentioned some MCLK clock. But no more info about this MCLK clock is given. What is its period? I need it to compute SD_CLK frequency.

BR
Martin

P.S.
I beleive this is a typical copy & paste error. I would do the same to take pl180/181 TRM and copy most of its part to the UM. However you should mention at least that you have connected the MCLK to PCLK. I hope I did not overlook it in the UM.

Re: LPC1788 SD card interface MCLK clock

lpcware — Wed, 15 Jun 2016 17:34:19 GMT

Content originally posted in LPCWare by wmues on Thu Aug 20 11:02:17 MST 2015
MCLK ist the CPU core frequency.

Re: LPC1788 SD card interface MCLK clock

lpcware — Wed, 15 Jun 2016 17:34:20 GMT

Content originally posted in LPCWare by wella-tabor on Fri Aug 21 00:09:35 MST 2015

Quote: wmues
MCLK ist the CPU core frequency.

Are you sure? What about to set CPU to 120MHz, PCLKDIV = 4? Would it work? The property f(PCLK) >= 3/8 f(MCLK) is not satisfied (PL181) because 30 is not >= 45.
I did not see such limitation in the UM or datasheet for the LPC1788. And I am pretty sure that LPC1788 uses PL180 or PL181.

BR
Martin

Re: LPC1788 SD card interface MCLK clock

lpcware — Wed, 15 Jun 2016 17:34:20 GMT

Content originally posted in LPCWare by wmues on Fri Aug 21 04:07:10 MST 2015
I do not know where you have read about MLCK.

I set the frequency of the SD card with the following function:

// set the clock
static void lpc178x_mmc_clock(long frequency)
{
    LPC_MCI->CLOCK = (LPC_MCI->CLOCK & ~0xFF) | (PeripheralClock / (frequency *2)) | 0x300;   // Clock enabled and PwrSave
}

So MCI clock is driven by Peripheral Clock.

Re: LPC1788 SD card interface MCLK clock

lpcware — Wed, 15 Jun 2016 17:34:21 GMT

Content originally posted in LPCWare by wella-tabor on Sun Aug 23 09:00:38 MST 2015

Quote: wmues
I do not know where you have read about MLCK.

I have read it here: UM10470, Rev. 3.1, page 463.

Table 348. MCI Clock Control register (CLOCK - address 0x400C 0004) bit description
Bit Symbol
7:0 CLKDIV
Value Description
Reset
Value
Bus clock period:
0
SD_CLK frequency = MCLK / [2 ́(ClkDiv+1)].
..............

Note: After a data write, data cannot be written to this register for three MCLK clock
periods plus two PCLK clock periods.

BR
Martin