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    <title>topic LPC4078: using 16bit bus width external SDRAM as program memory in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4078-using-16bit-bus-width-external-SDRAM-as-program-memory/m-p/682384#M27453</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm developing an application using&amp;nbsp;LPC4078FBD208 and an Alliance&amp;nbsp;AS4C4M16SA SDRAM IC as external memory. After bootup I'm going to load the program data from a SD card, write it on the external memory and switch CPU context to execute from the external memory.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;As M4 instructions are 32bit, the SDRAM 16bit bus width represent a problem for this scenario? The memory max clock is 144MHz, therefore I'll need two clock cycles (assuming that MCU core clock will be 120MHz) to fetch an entire instruction through EMC, will I have to reduce the CPU core clock to 60MHz to work with this setup?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 03 Jul 2017 20:25:11 GMT</pubDate>
    <dc:creator>otavioborges</dc:creator>
    <dc:date>2017-07-03T20:25:11Z</dc:date>
    <item>
      <title>LPC4078: using 16bit bus width external SDRAM as program memory</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4078-using-16bit-bus-width-external-SDRAM-as-program-memory/m-p/682384#M27453</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm developing an application using&amp;nbsp;LPC4078FBD208 and an Alliance&amp;nbsp;AS4C4M16SA SDRAM IC as external memory. After bootup I'm going to load the program data from a SD card, write it on the external memory and switch CPU context to execute from the external memory.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;As M4 instructions are 32bit, the SDRAM 16bit bus width represent a problem for this scenario? The memory max clock is 144MHz, therefore I'll need two clock cycles (assuming that MCU core clock will be 120MHz) to fetch an entire instruction through EMC, will I have to reduce the CPU core clock to 60MHz to work with this setup?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 03 Jul 2017 20:25:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4078-using-16bit-bus-width-external-SDRAM-as-program-memory/m-p/682384#M27453</guid>
      <dc:creator>otavioborges</dc:creator>
      <dc:date>2017-07-03T20:25:11Z</dc:date>
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    <item>
      <title>Re: LPC4078: using 16bit bus width external SDRAM as program memory</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4078-using-16bit-bus-width-external-SDRAM-as-program-memory/m-p/682385#M27454</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A _jive_internal="true" data-content-finding="Community" data-userid="227997" data-username="otavioborges" href="https://community.nxp.com/people/otavioborges"&gt;Otavio Borges&lt;/A&gt; ,&lt;/P&gt;&lt;DIV style="color: #000000; font-family: 微软雅黑; font-size: 14px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 21px; orphans: auto; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff;"&gt;&lt;SPAN style="background-color: inherit; line-height: 1.5; font-family: 微软雅黑,sans-serif;"&gt;Thank you for your interest in NXP Semiconductor products and&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV style="color: #000000; font-family: 微软雅黑; font-size: 14px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 1.5; orphans: auto; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff;"&gt;&lt;SPAN style="background-color: inherit; font-family: 微软雅黑,sans-serif;"&gt;for the opportunity to serve you.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV style="color: #000000; font-family: 微软雅黑; font-size: 14px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 1.5; orphans: auto; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff;"&gt;&lt;SPAN style="background-color: inherit; font-family: 微软雅黑,sans-serif;"&gt;As M4 instructions are 32bit, the SDRAM 16bit bus width represent a problem for this scenario? The memory max clock is 144MHz, therefore I'll need two clock cycles (assuming that MCU core clock will be 120MHz) to fetch an entire instruction through EMC, will I have to reduce the CPU core clock to 60MHz to work with this setup?&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV style="color: #000000; font-family: 微软雅黑; font-size: 14px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 1.5; orphans: auto; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff;"&gt;&lt;SPAN style="background-color: inherit; font-family: 微软雅黑,sans-serif;"&gt;-- I don't think so.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV style="color: #000000; font-family: 微软雅黑; font-size: 14px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 1.5; orphans: auto; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff;"&gt;Have a great day,&lt;/DIV&gt;&lt;P&gt;TIC&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 05 Jul 2017 04:09:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4078-using-16bit-bus-width-external-SDRAM-as-program-memory/m-p/682385#M27454</guid>
      <dc:creator>jeremyzhou</dc:creator>
      <dc:date>2017-07-05T04:09:36Z</dc:date>
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      <title>Re: LPC4078: using 16bit bus width external SDRAM as program memory</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4078-using-16bit-bus-width-external-SDRAM-as-program-memory/m-p/682386#M27455</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;According to the users manual, the max EMC clock (I'm not 100% sure, but I read the "dynamic EMC timing" that Tmin is 12.5 nSec) is 80 MHz. I think you will have to set the EMC clock divider to 2 to get 60 MHz for the EMC if runinng the CPU at 120 MHz? &amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 05 Jul 2017 07:14:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4078-using-16bit-bus-width-external-SDRAM-as-program-memory/m-p/682386#M27455</guid>
      <dc:creator>carstengroen</dc:creator>
      <dc:date>2017-07-05T07:14:24Z</dc:date>
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