topic Re: LPC1788 SPI SCK in LPC Microcontrollers https://community.nxp.com/t5/LPC-Microcontrollers/LPC1788-SPI-SCK/m-p/670140#M26808 <HTML><HEAD></HEAD><BODY><P>Hello,</P><P></P><P>The minimum clock cycle time, and therefore the maximum frequency of the SSP in master mode, is limited by the pin electronics to the value given. The SSP block should not be configured to generate a clock faster than that. At and below the maximum frequency, Tcy(clk) = (SSPCLKDIV&nbsp; x&nbsp; (1 + SCR) x CPSDVSR) / fmain. 5The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).</P><P><BR />Have a great day,<BR />Sol </P><P></P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Fri, 02 Jun 2017 20:53:17 GMT soledad 2017-06-02T20:53:17Z LPC1788 SPI SCK https://community.nxp.com/t5/LPC-Microcontrollers/LPC1788-SPI-SCK/m-p/670139#M26807 <HTML><HEAD></HEAD><BODY><P>Recently,I am debugging the spi communitcation of LPC1788 . In master mode, how much&nbsp;is&nbsp;the max frequency of SPI ??</P></BODY></HTML> Thu, 01 Jun 2017 06:41:31 GMT https://community.nxp.com/t5/LPC-Microcontrollers/LPC1788-SPI-SCK/m-p/670139#M26807 ljun_cdut 2017-06-01T06:41:31Z Re: LPC1788 SPI SCK https://community.nxp.com/t5/LPC-Microcontrollers/LPC1788-SPI-SCK/m-p/670140#M26808 <HTML><HEAD></HEAD><BODY><P>Hello,</P><P></P><P>The minimum clock cycle time, and therefore the maximum frequency of the SSP in master mode, is limited by the pin electronics to the value given. The SSP block should not be configured to generate a clock faster than that. At and below the maximum frequency, Tcy(clk) = (SSPCLKDIV&nbsp; x&nbsp; (1 + SCR) x CPSDVSR) / fmain. 5The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).</P><P><BR />Have a great day,<BR />Sol </P><P></P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Fri, 02 Jun 2017 20:53:17 GMT https://community.nxp.com/t5/LPC-Microcontrollers/LPC1788-SPI-SCK/m-p/670140#M26808 soledad 2017-06-02T20:53:17Z