<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: LPC11U6x flash accelerator and function moving from flash to RAM in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC11U6x-flash-accelerator-and-function-moving-from-flash-to-RAM/m-p/648883#M25748</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A _jive_internal="true" data-content-finding="Community" data-userid="285632" data-username="pberna" href="https://community.nxp.com/people/pberna"&gt;Paolo Bernasconi&lt;/A&gt;，&lt;/P&gt;&lt;P style="background: white;"&gt;&lt;SPAN style="color: black;"&gt;1) Does LPC11U6x has a flash accelerator ?&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;BR style="background-color: inherit;" /&gt; No, it doesn't have it.&lt;BR style="background-color: inherit;" /&gt; 2) If I run the CPU at 50Mhz what is the average CPI fo fetch an instruction form the flash ?&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;BR style="background-color: inherit;" /&gt; &lt;SPAN style="background-color: inherit;"&gt;The cycle counts is depend the particular instruction and wait-states configuration.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="background: white;"&gt;&lt;SPAN style="color: black;"&gt;&lt;SPAN style="background-color: inherit;"&gt;I'&lt;/SPAN&gt;&lt;SPAN style="background-color: inherit;"&gt;ve attached the&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="background-color: inherit;"&gt;Cortex&amp;nbsp;0+Technical&amp;nbsp;Reference&amp;nbsp;Manual and you&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="background-color: inherit;"&gt;can find&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN style="background-color: inherit;"&gt;the Cortex-M0+ instructions and their cycle counts in the Table 3-1.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="background: white;"&gt;&lt;SPAN style="background-color: inherit; color: black;"&gt;3)In the user manual I see the register that set a number of wait cycle depending on the CPU frequency (3 cycles if CPU ? 50Mhz) In case no flash accelerator is available is this the number of wait cycle I have to wait ?&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="background: white;"&gt;&lt;SPAN style="background-color: inherit; color: black;"&gt;Yes.&lt;BR style="background-color: inherit;" /&gt; 4) How is possible to move an ISR function from flash to RAM using LPCxpresso copy it automatically by the c startup code ?&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="background-color: inherit; color: black;"&gt;I've attached the application note: AN11511, it has illustrated the approach of relocating the interrupt table to the SRAM in the section 5.1.4.&lt;BR /&gt; &lt;/SPAN&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Ping&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 03 Jan 2017 01:47:09 GMT</pubDate>
    <dc:creator>jeremyzhou</dc:creator>
    <dc:date>2017-01-03T01:47:09Z</dc:date>
    <item>
      <title>LPC11U6x flash accelerator and function moving from flash to RAM</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC11U6x-flash-accelerator-and-function-moving-from-flash-to-RAM/m-p/648882#M25747</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1) Does LPC11U6x has a flash accelerator ?&lt;/P&gt;&lt;P&gt;2) If I run the CPU at 50Mhz what is the average CPI fo fetch an instruction form the flash ?&lt;/P&gt;&lt;P&gt;3)In the user manual I see the register that set a number of wait cycle depending on the CPU frequency (3 cycles if CPU ? 50Mhz) In case no flash accelerator is available is this the number of wait cycle I have to wait ?&lt;/P&gt;&lt;P&gt;4) How is possible to move an ISR function from flash to RAM using LPCxpresso&amp;nbsp;copy it automatically by the c&amp;nbsp;startup&amp;nbsp;code ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Paolo&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Dec 2016 11:03:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC11U6x-flash-accelerator-and-function-moving-from-flash-to-RAM/m-p/648882#M25747</guid>
      <dc:creator>pberna</dc:creator>
      <dc:date>2016-12-29T11:03:21Z</dc:date>
    </item>
    <item>
      <title>Re: LPC11U6x flash accelerator and function moving from flash to RAM</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC11U6x-flash-accelerator-and-function-moving-from-flash-to-RAM/m-p/648883#M25748</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A _jive_internal="true" data-content-finding="Community" data-userid="285632" data-username="pberna" href="https://community.nxp.com/people/pberna"&gt;Paolo Bernasconi&lt;/A&gt;，&lt;/P&gt;&lt;P style="background: white;"&gt;&lt;SPAN style="color: black;"&gt;1) Does LPC11U6x has a flash accelerator ?&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;BR style="background-color: inherit;" /&gt; No, it doesn't have it.&lt;BR style="background-color: inherit;" /&gt; 2) If I run the CPU at 50Mhz what is the average CPI fo fetch an instruction form the flash ?&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;BR style="background-color: inherit;" /&gt; &lt;SPAN style="background-color: inherit;"&gt;The cycle counts is depend the particular instruction and wait-states configuration.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="background: white;"&gt;&lt;SPAN style="color: black;"&gt;&lt;SPAN style="background-color: inherit;"&gt;I'&lt;/SPAN&gt;&lt;SPAN style="background-color: inherit;"&gt;ve attached the&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="background-color: inherit;"&gt;Cortex&amp;nbsp;0+Technical&amp;nbsp;Reference&amp;nbsp;Manual and you&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="background-color: inherit;"&gt;can find&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN style="background-color: inherit;"&gt;the Cortex-M0+ instructions and their cycle counts in the Table 3-1.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="background: white;"&gt;&lt;SPAN style="background-color: inherit; color: black;"&gt;3)In the user manual I see the register that set a number of wait cycle depending on the CPU frequency (3 cycles if CPU ? 50Mhz) In case no flash accelerator is available is this the number of wait cycle I have to wait ?&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="background: white;"&gt;&lt;SPAN style="background-color: inherit; color: black;"&gt;Yes.&lt;BR style="background-color: inherit;" /&gt; 4) How is possible to move an ISR function from flash to RAM using LPCxpresso copy it automatically by the c startup code ?&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="background-color: inherit; color: black;"&gt;I've attached the application note: AN11511, it has illustrated the approach of relocating the interrupt table to the SRAM in the section 5.1.4.&lt;BR /&gt; &lt;/SPAN&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Ping&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 03 Jan 2017 01:47:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC11U6x-flash-accelerator-and-function-moving-from-flash-to-RAM/m-p/648883#M25748</guid>
      <dc:creator>jeremyzhou</dc:creator>
      <dc:date>2017-01-03T01:47:09Z</dc:date>
    </item>
  </channel>
</rss>

