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    <title>LPC MicrocontrollersのトピックLPC4330 and LPC1830 Errata OTP.2 Power and Reset Sequencing</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4330-and-LPC1830-Errata-OTP-2-Power-and-Reset-Sequencing/m-p/644283#M25465</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are using LPC4330FET180 in our design and still have die revC in stock. &amp;nbsp;Please help us understand this OTP.2 issue discussed in "&lt;A href="http://www.nxp.com/documents/errata_sheet/ES_LPC43X0.pdf?fasp=1&amp;amp;WT_TYPE=Errata&amp;amp;WT_VENDOR=FREESCALE&amp;amp;WT_FILE_FORMAT=pdf&amp;amp;WT_ASSET=Documentation&amp;amp;fileExt=.pdf"&gt;Errata sheet LPC4370, LPC4350, LPC4330, LPC4320, LPC4310&lt;/A&gt;" by sharing more detail about the following:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;What is the nature of the "repeated power cycling" that might cause this erroneous programming? &amp;nbsp;How many power cycles and at what frequency of toggling the power causes the issue?&lt;/LI&gt;&lt;LI&gt;&lt;SPAN&gt;Is the 2 ms delay in the suggested timing diagram intended to be minimum, nominal or maximum? &amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;What tolerances are permitted on the suggested 2 ms delay?&lt;/SPAN&gt;&lt;/LI&gt;&lt;LI&gt;Are there any issues if the delays are much longer than 2ms, say up to 20 - 30 ms?&lt;/LI&gt;&lt;LI&gt;What is the voltage at which nRESET is deasserted? &amp;nbsp;I've assumed VIH 0.8 x (Vps-0.35) based on datasheet. &amp;nbsp;However, in our circuit, I see input current jump suggesting the IRC oscillator is starting when nRESET gets to about half rail.&lt;/LI&gt;&lt;LI&gt;I think the example delay circuit will produce timings somewhat different than the conceptual waveform for the workaround. &amp;nbsp;In particular the VDDIO and RESETN voltages will not remain at zero until after VDDREG, VDDA have reached their full value as drawn. &amp;nbsp;Please advise if a delay scheme which clamps the VDDIO and RESETN at 0 V for the 2ms delay is essential.&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;Thank you for your help and comments.&lt;/P&gt;&lt;P&gt;--&amp;nbsp;&lt;/P&gt;&lt;P&gt;Neil&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 17 Oct 2016 22:20:48 GMT</pubDate>
    <dc:creator>neilallison</dc:creator>
    <dc:date>2016-10-17T22:20:48Z</dc:date>
    <item>
      <title>LPC4330 and LPC1830 Errata OTP.2 Power and Reset Sequencing</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4330-and-LPC1830-Errata-OTP-2-Power-and-Reset-Sequencing/m-p/644283#M25465</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are using LPC4330FET180 in our design and still have die revC in stock. &amp;nbsp;Please help us understand this OTP.2 issue discussed in "&lt;A href="http://www.nxp.com/documents/errata_sheet/ES_LPC43X0.pdf?fasp=1&amp;amp;WT_TYPE=Errata&amp;amp;WT_VENDOR=FREESCALE&amp;amp;WT_FILE_FORMAT=pdf&amp;amp;WT_ASSET=Documentation&amp;amp;fileExt=.pdf"&gt;Errata sheet LPC4370, LPC4350, LPC4330, LPC4320, LPC4310&lt;/A&gt;" by sharing more detail about the following:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;What is the nature of the "repeated power cycling" that might cause this erroneous programming? &amp;nbsp;How many power cycles and at what frequency of toggling the power causes the issue?&lt;/LI&gt;&lt;LI&gt;&lt;SPAN&gt;Is the 2 ms delay in the suggested timing diagram intended to be minimum, nominal or maximum? &amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;What tolerances are permitted on the suggested 2 ms delay?&lt;/SPAN&gt;&lt;/LI&gt;&lt;LI&gt;Are there any issues if the delays are much longer than 2ms, say up to 20 - 30 ms?&lt;/LI&gt;&lt;LI&gt;What is the voltage at which nRESET is deasserted? &amp;nbsp;I've assumed VIH 0.8 x (Vps-0.35) based on datasheet. &amp;nbsp;However, in our circuit, I see input current jump suggesting the IRC oscillator is starting when nRESET gets to about half rail.&lt;/LI&gt;&lt;LI&gt;I think the example delay circuit will produce timings somewhat different than the conceptual waveform for the workaround. &amp;nbsp;In particular the VDDIO and RESETN voltages will not remain at zero until after VDDREG, VDDA have reached their full value as drawn. &amp;nbsp;Please advise if a delay scheme which clamps the VDDIO and RESETN at 0 V for the 2ms delay is essential.&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;Thank you for your help and comments.&lt;/P&gt;&lt;P&gt;--&amp;nbsp;&lt;/P&gt;&lt;P&gt;Neil&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 17 Oct 2016 22:20:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4330-and-LPC1830-Errata-OTP-2-Power-and-Reset-Sequencing/m-p/644283#M25465</guid>
      <dc:creator>neilallison</dc:creator>
      <dc:date>2016-10-17T22:20:48Z</dc:date>
    </item>
    <item>
      <title>Re: LPC4330 and LPC1830 Errata OTP.2 Power and Reset Sequencing</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4330-and-LPC1830-Errata-OTP-2-Power-and-Reset-Sequencing/m-p/644284#M25466</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please check the belos threads and let me know if this helps,&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; font-size: 14px; padding: 0px;"&gt;&lt;A _jive_internal="true" data-containerid="51919" data-containertype="700" data-objectid="437538" data-objecttype="1" href="https://community.nxp.com/thread/437538" style="color: #5e89c1; background-color: transparent; border: 0px; font-weight: inherit; font-size: 14px; padding: 1px 0px 1px calc(12px + 0.35ex);"&gt;OTP Errata on LPC43xx Rev C&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; font-size: 14px; padding: 0px;"&gt;&lt;A _jive_internal="true" data-containerid="51919" data-containertype="700" data-objectid="432570" data-objecttype="1" href="https://community.nxp.com/thread/432570" style="color: #5e89c1; background-color: transparent; border: 0px; font-weight: inherit; font-size: 14px; padding: 1px 0px 1px calc(12px + 0.35ex);"&gt;Support to detect OPT2 issue of processors with version D&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; font-size: 14px;"&gt;Have a great day,&lt;BR /&gt;Sol&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; font-size: 14px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; font-size: 14px;"&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 10 Nov 2016 18:15:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4330-and-LPC1830-Errata-OTP-2-Power-and-Reset-Sequencing/m-p/644284#M25466</guid>
      <dc:creator>soledad</dc:creator>
      <dc:date>2016-11-10T18:15:06Z</dc:date>
    </item>
    <item>
      <title>Re: LPC4330 and LPC1830 Errata OTP.2 Power and Reset Sequencing</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4330-and-LPC1830-Errata-OTP-2-Power-and-Reset-Sequencing/m-p/644285#M25467</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Sol, &amp;nbsp;&lt;/P&gt;&lt;P&gt;I'm sorry the links you provide give me an error&amp;nbsp;&lt;/P&gt;&lt;P&gt;"Unauthorized&lt;BR /&gt;This place or content does not exist or access to it is restricted. If you think this is a mistake, please contact your administrator or the person who directed you here."&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Kind regards&lt;/P&gt;&lt;P&gt;Neil&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 12 Nov 2016 01:17:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4330-and-LPC1830-Errata-OTP-2-Power-and-Reset-Sequencing/m-p/644285#M25467</guid>
      <dc:creator>neilallison</dc:creator>
      <dc:date>2016-11-12T01:17:30Z</dc:date>
    </item>
    <item>
      <title>Re: LPC4330 and LPC1830 Errata OTP.2 Power and Reset Sequencing</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4330-and-LPC1830-Errata-OTP-2-Power-and-Reset-Sequencing/m-p/644286#M25468</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Please check the comments below,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/9808i3534B623023726F2/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/9852i198E583D2CD28E54/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Sol&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 16 Dec 2016 17:04:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4330-and-LPC1830-Errata-OTP-2-Power-and-Reset-Sequencing/m-p/644286#M25468</guid>
      <dc:creator>soledad</dc:creator>
      <dc:date>2016-12-16T17:04:04Z</dc:date>
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