Problem setting CCLKDIV register in LPC1778

carstengroen — Fri, 04 Nov 2016 08:24:26 GMT

I have a system running on a LPC1778 (using SDRAM, USB etc etc). All is working fine so far, stable etc.

However, I'm trying to do "clock throttling" of the CPU and thats where things go downhill :smileywink:

The system starts up running 120 MHz (EMCCLK for the SDRAM runs at 1/2 speed so 60 MHz, PBOOST set to 0x03). I then have a function where I can set the CCLKDIV register to divide the CPU clock with either 1, 2 or 4 (giving me 120, 60 or 30 MHz).

This is needed to avoid one of the errata where IAP will fail on 5% of devices if running at 120 MHz and to conserve power at certain times. PCLKDIV is always set to divide by 4.

When changing the divider, I get very often, around 50% of the time, a hard fault. It does not depend on what divider I select, if I go to divide by 2 and then back to 1 or to 4, it can hardfault, there is no consistency in this (and sometimes I can change divider 1 or 2 times successfully and at the 3rd time it faults).

The cause and information of the hardfault differs between different runs, so not very consistent. If I select the same divider as currently selected (basically just rewriting the CCLKDIV register with the same value, no faults are triggered). The PC points to a SVC handler (the change is done via a call thru SVC). None of the other information makes much sense to me..

Is there any thing I must consider when writing the CCLKDIV register ?

One example of hardfault:

161104 09:01:17.627::E:[diagnose.c:224] R0=0xA01C8470/-1608743824
161104 09:01:17.709::E:[diagnose.c:225] R1=0x01000000/16777216
161104 09:01:18.197::E:[diagnose.c:226] R2=0xFFFFFFE0/-32
161104 09:01:18.278::E:[diagnose.c:227] R3=0xA01C8528/-1608743640
161104 09:01:18.400::E:[diagnose.c:229] R12=0x0004DBAD
161104 09:01:18.891::E:[diagnose.c:230] LR [R14]=0xFFFFFFFD
161104 09:01:18.972::E:[diagnose.c:231] PC [R15]=0x0002031A
161104 09:01:19.075::E:[diagnose.c:233] PSR=0x0100000B
161104 09:01:19.135::E:[diagnose.c:236] CFSR (Config. Fault SR)=0x00008200
161104 09:01:19.645::E:[diagnose.c:245] :BusFault->Bus Fault Address Register (BFAR) holds a valid address=0x00FFFFFE
161104 09:01:19.726::E:[diagnose.c:254] HFSR (Hard Fault SR)=0x40000000
161104 09:01:19.809::E:[diagnose.c:258] :FORCED, Bus fault/Memory management fault/usage fault
161104 09:01:19.891::E:[diagnose.c:263] DFSR (Debug Fault SR)=0x00000008
161104 09:01:20.382::E:[diagnose.c:265] AFSR (Auxiliary Fault SR)=0x00000000
161104 09:01:20.484::E:[diagnose.c:266] SCB->SHCSR (System Handler Control and State R (exception))=0x00000080

and another:

161104 09:11:46.120::E:[diagnose.c:224] R0=0x00000001/1
161104 09:11:46.181::E:[diagnose.c:225] R1=0x00000000/0
161104 09:11:46.711::E:[diagnose.c:226] R2=0x00000000/0
161104 09:11:46.773::E:[diagnose.c:227] R3=0x0004D74D/317261
161104 09:11:46.874::E:[diagnose.c:229] R12=0x00024E01
161104 09:11:46.936::E:[diagnose.c:230] LR [R14]=0x00000000
161104 09:11:47.424::E:[diagnose.c:231] PC [R15]=0x40000000
161104 09:11:47.525::E:[diagnose.c:233] PSR=0x4000C000
161104 09:11:47.606::E:[diagnose.c:236] CFSR (Config. Fault SR)=0x00020000
161104 09:11:47.790::E:[diagnose.c:254] HFSR (Hard Fault SR)=0x40000000
161104 09:11:48.320::E:[diagnose.c:258] :FORCED, Bus fault/Memory management fault/usage fault
161104 09:11:48.381::E:[diagnose.c:263] DFSR (Debug Fault SR)=0x00000008
161104 09:11:48.461::E:[diagnose.c:265] AFSR (Auxiliary Fault SR)=0x00000000
161104 09:11:48.563::E:[diagnose.c:266] SCB->SHCSR (System Handler Control and State R (exception))=0x00000000

Re: Problem setting CCLKDIV register in LPC1778

carstengroen — Fri, 04 Nov 2016 11:10:47 GMT

Some more testing has been done, it seems that changing from CCLKDIV 1 to 4 and back works every time! It is only going to CCLKDIV 2 that there is a problem (around 50% of the time). If this is any help or not I don't know.....

Re: Problem setting CCLKDIV register in LPC1778

carstengroen — Sat, 05 Nov 2016 12:24:15 GMT

Bump....

Anyone know why a CCLKDIV value of 2 crashes the system and a CCLKDIV of 4 (and 1) does not ?

Re: Problem setting CCLKDIV register in LPC1778

jeremyzhou — Mon, 07 Nov 2016 02:47:43 GMT

Hi Carsten Groen,

After had a brief look through the issue description, I was wondering if you can share a simple demo that I can replicate the issue on my site.

I'm looking forward to your reply.

Have a great day,
Ping

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Re: Problem setting CCLKDIV register in LPC1778

carstengroen — Mon, 07 Nov 2016 05:35:29 GMT

Thanks Ping,

I will see if I can cook something together that will show the same behavior. In the meantime, is there any reason you can think of why there is a problem the way I do it, ie is there any logical reason that this should be a problem ?

I also tried running the CPU at 96 MHz, and the result was the same, a CCLKDIV of 2 crashes the system, and 1 or 4 does not.

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Problem setting CCLKDIV register in LPC1778

Re: Problem setting CCLKDIV register in LPC1778

Re: Problem setting CCLKDIV register in LPC1778

Re: Problem setting CCLKDIV register in LPC1778

Re: Problem setting CCLKDIV register in LPC1778