topic Re: EMC with SRAM misses some Chipselects in LPC Microcontrollers

EMC with SRAM misses some Chipselects

lpcware — Wed, 15 Jun 2016 17:31:30 GMT

Content originally posted in LPCWare by broky on Wed May 13 09:00:18 MST 2015
Hi everybody,
at the moment I'm trying to connect a IS61WV12816DBLL-10 SRAM to the EMC of my LPC1788 custom board. If I use the EMC in 16 wide mode, I sometimes have problems writing values to the SRAM. One of 100 bytes will be skipped. A look on the scope shows why (See attachment). The chip select active low signal is missing time by time. But at the moment there is no other memory on the bus. The SRAM contains my framebuffer that is displayed by the LCD Peripheral. The LCD part is working properly because in 8 bit EMC mode the image is correct and the scope does not show any missing chip selects.

The bus is running at 96MHz like you can see in the timing register screenshot attachment. I also post my EMC configuration registers for 16 bit mode. Does anyone have an idea what's going wrong here?

Many thanks,
Jonathan

Re: EMC with SRAM misses some Chipselects

lpcware — Wed, 15 Jun 2016 17:31:31 GMT

Content originally posted in LPCWare by MikeSimmonds on Wed May 13 11:32:36 MST 2015
I thought that the maximum EMC clock speed is 80 MHz [from the 1778/1788 datasheet].
Perhaps running above the rated maximum [96 MHz] is causing your problems.

Regards, Mike

Re: EMC with SRAM misses some Chipselects

lpcware — Wed, 15 Jun 2016 17:31:31 GMT

Content originally posted in LPCWare by mc on Wed May 13 13:04:00 MST 2015
Hi broky,
As mentioned by Mike the maximum EMC speed is 80MHz. You have two below options.

1) Run Core at 120MHz and EMC at 80MHz
or
2) Run Core at 80MHz and run EMC at 80MHz.

Can you please check if project works with above mentioned clock settings?

Edit: As pointed by MIke in below reply Option 1 had typo. The two options are:

1) Run Core at 120MHz and EMC at 60MHz
or
2) Run Core at 80MHz and run EMC at 80MHz.

Thanks Mike for pointing it out.

Re: EMC with SRAM misses some Chipselects

lpcware — Wed, 15 Jun 2016 17:31:32 GMT

Content originally posted in LPCWare by MikeSimmonds on Thu May 14 02:48:33 MST 2015

Quote: mc
Hi broky,
As mentioned by Mike the maximum EMC speed is 80MHz. You have two below options.

1) Run Core at 120MHz and EMC at 80MHz
or
2) Run Core at 80MHz and run EMC at 80MHz.

Can you please check if project works with above mentioned clock settings?

Typo in "1)" Should be Run Core as 120MHz and EMC at 60MHz
I.e EMC = CCLK/2

For 2) EMC = CCLK (divide by 1)

Regards, Mike

Re: EMC with SRAM misses some Chipselects

lpcware — Wed, 15 Jun 2016 17:31:32 GMT

Content originally posted in LPCWare by broky on Mon May 18 00:16:34 MST 2015
Thank you for your answers. I modified my code using LPC_SC->EMCCLKSEL = 1 but nothing really changed. The bus should run at 48MHz now. I must have missed this important speed constraint in the datasheet. I didn't alter the timings for the memory. So I'm still wondering what's going on.