topic Re: LPC1112 - hardfault on PDRUNCFG register write in LPC Microcontrollers

LPC1112 - hardfault on PDRUNCFG register write

danielkowalski — Sat, 04 Feb 2017 01:39:52 GMT

Hello,

I encountered strange problem with LPC1112 MCU when creating new design.

MCU mysteriously hard-faulted before reaching main, so I started debugging startup code (this works perfectly fine) and found problematic line in CMSIS source (system_LPC11xx.c):

LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */

After reading through manual I found that some reserved bits need to be set to 1 in PDRUNCFG during write,

I tried setting register value to reset value (with required reserved bits), before even calling SystemInit.

Result is still the same - I get HardFault even with simple write to register:

LPC_SYSCON->PDRUNCFG = 0b1110110111110000;

The only thing happening before that is filling bss with zeros and copying data section to RAM.

what might be wrong with this? (I cannot configure system clock)

MCU is LPC1112FHI33/202.5

Daniel

Re: LPC1112 - hardfault on PDRUNCFG register write

Dezheng_Tang — Wed, 08 Feb 2017 00:50:16 GMT

Daniel,

There is a possibilty that you used SYS OSC as the clock source for SYSPLLCLKSEL already and MAINCLK is derived from SYS OSC already, then you power down the SYS OSC in PDRUNCFG, you will get the hard fault.

If you use IRC as the clock source in SYSPLLCLK and MAINCLK, then, it will be OK to power down SYS OSC to lower the overall power consumption. Try this:

http://www.nxp.com/products/software-and-tools/hardware-development-tools/lpcxpresso-boards/lpcopen-software-development-platform-lpc11xx:LPCOPEN-SOFTWARE-FOR-LPC11XX

Re: LPC1112 - hardfault on PDRUNCFG register write

danielkowalski — Thu, 09 Feb 2017 14:51:17 GMT

Hello,

I found the problem - Code was compiled for wrong core (facepalm).

I copied project from earlier revision, but I forgot that it used Cortex-m3 chip and LPC1112 is Cortex-M0.

Copynig data and zeroing BSS worked fine because it only used instructions supported by both cores, but when it came to writing registers

everything blew up.

Thanks for the help,

Daniel