topic Re: ADC PCLK for LPC1114fn28/102 in LPC Microcontrollers

ADC PCLK for LPC1114fn28/102

austinpalanca — Fri, 03 Feb 2017 17:55:51 GMT

My friend and I cannot seem to find a solid answer, neither through the user manual nor the datasheet. What is the frequency of the PCLK for the ADC block on the LPC1114fn28/102? The more information the better!

Thank you :smileyhappy:

Austin

Re: ADC PCLK for LPC1114fn28/102

dirceurodrigues — Mon, 06 Feb 2017 00:43:33 GMT

As stated on Users's Manual (ADC chapter):

"The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which
should be less than or equal to 4.5 MHz. Typically, software should program the smallest
value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such
as a high-impedance analog source) a slower clock may be desirable."

The maximum PCLK is around 48 MHz (the exact value depends on your specific setup and clock source, PLL, interrnal RC oscillator,...).

Re: ADC PCLK for LPC1114fn28/102

austinpalanca — Mon, 06 Feb 2017 18:56:04 GMT

Thank you very much! We are going to use the IRC (by default) which operates at about 12 Mhz, then divide it twice, once from PLL and once with the ADC clkdiv to achieve our results.