LPC Microcontrollers中的主题 Re: LPC43xx EMC Buffer enabled

LPC43xx EMC Buffer enabled

skysky — Tue, 25 Oct 2016 07:20:44 GMT

i use the lpc4353 EMC-CS0 driver the K9F1G08U0E nand flash.

when i set the register:Static Memory Configuration registers (STATICCONFIG[0:3],the bit 19

code is :

LPC_EMC->STATICCONFIG0 |= 1 << 19;

then,the chip K9F1G08U0E read/write error.

when i insert the delay() in the operation of K9F1G08U0E ,such as :

K9F1G08_CLE = K9FXX_READ_ID;
delay();
K9F1G08_ALE = 0;
delay();

a = K9F1G08_DATA;
delay();

b = K9F1G08_DATA;
delay();

c = K9F1G08_DATA;
delay();

the read/write is correct.

when i don't add code:LPC_EMC->STATICCONFIG0 |= 1 << 19;

the delay() is not need,the read/write is also correct.

Re: LPC43xx EMC Buffer enabled

Carlos_Mendoza — Fri, 28 Oct 2016 21:27:28 GMT

Hi sky,

All NAND Flash operations are initiated by issuing a command cycle. This is accomplished by placing the command on I/O[7:0], driving CE# LOW and CLE HIGH, then issuing a WE# clock. Commands, addresses, and data are clocked into the NAND Flash device on the rising edge of WE#. I don't think the buffers can be used, this is because the result will be taken from the buffers, and no physical read cycle will be initiated.

Please also notice that the EMC is not to designed to connect to parallel NAND flash, it is specified for SDR SDRAM and standard asynchronous static memory only. While it is possible to connect NAND to the static interface, abusing address lines as data/command selectors, this is neither specified nor recommended, and has a negative impact on the performance of the external memory bus.

We rather encourage customers to use the SPIFI interface to connect to quad SPI serial memory devices instead.

Hope it helps!

Best Regards,
Carlos Mendoza
Technical Support Engineer

Re: LPC43xx EMC Buffer enabled

skysky — Wed, 02 Nov 2016 08:09:07 GMT

thanks your reply

thank you