LPC MicrocontrollersのトピックRe: SPI interrupt RX FIFO one frame

SPI interrupt RX FIFO one frame

lpcware — Wed, 15 Jun 2016 19:26:18 GMT

Content originally posted in LPCWare by MrBool on Sat Jul 25 01:58:31 MST 2015
I'm using SPI in slave mode. I have found information in user manual that for LPC1114 interrupt can be enable when the Rx FIFO is at least half full. Because FIFO size is 8 frames. So I have to wait for 4 frames.
Is passible to enable interrupt for RX one frame only?

Re: SPI interrupt RX FIFO one frame

lpcware — Wed, 15 Jun 2016 19:26:19 GMT

Content originally posted in LPCWare by 1234567890 on Sat Jul 25 02:29:51 MST 2015
You can use RTIM in SSP0IMSC (if you have the time for).
Unfortunately RNE in SSP0SR doesn't raise an interrupt.

Re: SPI interrupt RX FIFO one frame

lpcware — Wed, 15 Jun 2016 19:26:19 GMT

Content originally posted in LPCWare by MrBool on Sat Jul 25 04:14:56 MST 2015
Thank you for reply.

In manual is "The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1])."

This equation is for bit rate. For example I have PCLK = 48MHz, CPSDVSR = 2 and SCR = 239.
This give me bit rate = 100kHz.

But what about timeout? How I can calculate it?

Re: SPI interrupt RX FIFO one frame

lpcware — Wed, 15 Jun 2016 19:26:20 GMT

Content originally posted in LPCWare by mysepp on Sat Jul 25 04:39:07 MST 2015
Please verify my calculation, but I would say:
1 bit takes 1 bit / (100000 bits/second) = 0.000001 seconds = 10 us
32 bits take 32 * 10us = 320 us
So the timeout is 320us?

Re: SPI interrupt RX FIFO one frame

lpcware — Wed, 15 Jun 2016 19:26:20 GMT

Content originally posted in LPCWare by MrBool on Sat Jul 25 04:58:57 MST 2015
Thank you mysepp.

You are right. I misunderstand "32 bits at". Now all is clear.