LPC MicrocontrollersのトピックRe: No interrupts (systick) on M0??

No interrupts (systick) on M0??

lpcware — Wed, 15 Jun 2016 19:22:25 GMT

Content originally posted in LPCWare by omegahacker on Thu Jun 12 18:37:06 MST 2014
OK, here we go again trying to get this M0 running. I have a dirt simple program that starts the systick and loops with an LED output based on a counter the ISR updates:

volatile uint8_t count = 0;

int main(void) {
  LPC_SCU->SFSPE_5 = 4;                 // GPIO
  LPC_GPIO_PORT->DIR[7] |= (1<<5);      // OUT
  LPC_GPIO_PORT->PIN[7] &= ~(1<<5);     // LED ON

  SysTick->LOAD = 100000;
  SysTick->VAL = 0;
  SysTick->CTRL = 0x00000007;

  NOPx(10000000);

  while (1) {
    if (count == 0) {
      LPC_GPIO_PORT->PIN[7] &= ~(1<<5);         // LED on
    } else {
      LPC_GPIO_PORT->PIN[7] |= (1<<5);          // LED off
    }
  }
}

void xPortSysTickHandler( void ) {
  count++;
}

When I run this directly on the M4, I get exactly what I expect: after an initial burst on, an LED that flickers.

When I load this onto the M0 (see previous threads), I get the LED starting on, a short delay (the NOPx before while()), then it goes off and stays off. The fact that the LED goes on then off proves that the code is indeed functioning. The fact that the LED stays dead proves that the interrupt is not firing.

Clearly I'm missing something, but I have no idea what. Help?

Re: No interrupts (systick) on M0??

lpcware — Wed, 15 Jun 2016 19:22:26 GMT

Content originally posted in LPCWare by sundarapandian on Thu Jun 12 19:18:36 MST 2014
In LPC43XX, the M0APP & M0SUB cores does not have systick timer. You could use RITimer.

Re: No interrupts (systick) on M0??

lpcware — Wed, 15 Jun 2016 19:22:27 GMT

Content originally posted in LPCWare by omegahacker on Thu Jun 12 20:09:42 MST 2014
Ummmmm, ok.

How would I actually go about finding this minor detail in the documentation?

Given that the SysTick is a) part of the per-core NVIC section, and b) pretty much assumed to exist 100% of the time (I've never seen a chip without it, nor does the book I just bought have any knowledge of a single chip without it), why is this something I have to find out the hard way??

Re: No interrupts (systick) on M0??

lpcware — Wed, 15 Jun 2016 19:22:28 GMT

Content originally posted in LPCWare by JohnR on Fri Jun 13 04:54:47 MST 2014
HI Sundarapandian,

That's a very poor reply.

In both M0Sub and M0App code, eg, cr_startup_lpc43xx-m0app.c and cmsis_43xx_m0app.h, SysTick() and its interrupt number are provided.

I also got caught by this problem and wasted a lot of time trying to understand why SysTick_Handler() did not seem to work.

Are there any more similar gotchas?

Please have the manuals updated.

JohnR.

Re: No interrupts (systick) on M0??

lpcware — Wed, 15 Jun 2016 19:22:29 GMT

Content originally posted in LPCWare by omegahacker on Sat Jun 14 08:48:06 MST 2014

Quote: omegahacker
How would I actually go about finding this minor detail in the documentation?

{sarcasm}I found it!{/sarcasm}

http://docs.lpcware.com/lpcopen/v1.03/group__u_cos-_i_i_i__43_x_x___m0___t_i_c_k.html

Re: No interrupts (systick) on M0??

lpcware — Wed, 15 Jun 2016 19:22:30 GMT

Content originally posted in LPCWare by Pacman on Sat Jun 14 11:28:29 MST 2014
I just looked in UM10503, to see if it said anything about it.
The only place it says anything about where SysTick is available, is in sectoin 1.2 "Features"...

Quote:
* Cortex-M4 Processor core
- ...
- ...
- [color=#080]System tick timer.[/color]
* Cortex-M0 Processor core (all LPC43xx parts)
- ...
- ...
- (nothing)
* Cortex-M0 Processor susbsystem core (LPC4370 parts only)
- ...
- ...
- (nothing)

...So: It's mentioned as existing for the M4, and SysTick is not mentioned for any of the M0 cores.

That means that the header files must be incorrect.

I have header files that #define M0_SysTick_IRQn too. I believe it should have been marked as "reserved" instead.

Re: No interrupts (systick) on M0??

lpcware — Wed, 15 Jun 2016 19:22:31 GMT

Content originally posted in LPCWare by omegahacker on Sun Jun 15 09:17:29 MST 2014

It's mentioned as existing for the M4, and SysTick is not mentioned for any of the M0 cores.

I do see that, but I don't consider that even remotely sufficient documentation.

My take is that while the SysTick is indeed "optional", 99+% of all chips out there implement it because it's such a fundamentally useful feature, and it takes all of a few dozen gates. If NXP is going to neglect to include such a feature, they need to be VERY EXPLICIT about the fact that something that's assumed to exist does not in fact actually exist.

Now my next question is: they suggest using the RITimer as a replacement for the M0APP - what about the M0SUB? It can respond to RITimer interrupts as well, but then who's responsible for clearing the interrupt? Is it edge or level triggered (I'm assuming level, since it actually has a "clear" flag). What if you have the RITimer at a lower priority and the M0APP fires and clears before the M0SUB can actually launch it's interrupt? This is why SysTick is a per-core component! Now one has to resort to some kind of semaphore BS in order to count who's caught the interrupt and who gets to clear it, etc. LAME!

Re: No interrupts (systick) on M0??

lpcware — Wed, 15 Jun 2016 19:22:31 GMT

Content originally posted in LPCWare by starblue on Mon Jun 16 05:12:32 MST 2014
I think the marketeers don't like to put negative information in the features list.

I didn't fall into this trap, but it caused me some extra work to verify that the SysTick doesn't exist, so I would also appreciate if this were spelled out clearly.

Similarly, 32 bit multiplication is the slow variant (32 cycles) on the M0 cores of the LPC43xx. It seems these are stripped down to the minimum when they are part of a multicore controller, in contrast to standalone M0 cores.

Quote: omegahacker
Now my next question is: they suggest using the RITimer as a replacement for the M0APP - what about the M0SUB? It can respond to RITimer interrupts as well, but then who's responsible for clearing the interrupt?

Pick one core. I use RITIMER to fire interrupts both on the M4 and the M0 on an LPC4357. The M4 is responsible for clearing the RITINT flag. Works well so far.

Quote: omegahacker
Is it edge or level triggered (I'm assuming level, since it actually has a "clear" flag). What if you have the RITimer at a lower priority and the M0APP fires and clears before the M0SUB can actually launch it's interrupt?

I think that is OK since each core has its own NVIC. My system wouldn't work otherwise (the interrupt has highest priority on the M4, but a rather low priority causing waits up to several µs on the M0. It fires every 25µs).

Jürgen