LPC MicrocontrollersのトピックRe: PWM dutycycle of 0% using SCTtimers?

PWM dutycycle of 0% using SCTtimers?

lpcware — Wed, 15 Jun 2016 19:22:58 GMT

Content originally posted in LPCWare by renskessener on Wed Feb 17 14:14:44 MST 2016
I want to make a PWM signal with a dutycycle from 0 – 100% in 64 steps.
(Actually I need 4 PWM’s but if one works I can make 4 work)
It must be possible to have 0% dutycycle.

I thought SCT timers would be the best choice.

I am new to LPC processors and I don’t understand (yet) all items in the user manual.
I use the LPC11U68 board as a vehicle to figure things out.
I used the example (in LPCopen) “ periph_SCT_PWM” as a guide.

Using STC1:
I set the MATCH0 and MATCHREL0 registers to 63 to represent PWM-cycle length.
I use MATCH1 and MATCHREL1 registers as the dutycycle register.
By changing the MATCHREL1 register to a new desired dutycycle, the MATCH1 register will follow the next cycle as I understand. It varies from 0 to 63.
EVENT[0] is used to signal a match for the PWM-cycle length and sets OUT0 to 1.
EVENT[1] is used to signal a match for the dutycycle and sets OUT0 to 0.
SCT_EVENT_0 and SCT_EVENT_1 bothe enable STATE0.
I think I do not need states.

It works, BUT at a dutycycle of 0, OUT0 still produces a pulse.
Probably because EVENT[0] take precedence or because, if MATCH1 == 0, EVENT[1] happens
At the first clockcycle.?????

Do I misunderstand the capabilities of the SCT-timers?
What do I do wrong?
Is there an example out there that makes a PWM that includes 0% dutycycle?

Thanks in advance

Re: PWM dutycycle of 0% using SCTtimers?

lpcware — Wed, 15 Jun 2016 19:22:59 GMT

Content originally posted in LPCWare by MarcVonWindscooting on Sat Feb 20 04:00:08 MST 2016
I'm working with LPC800 SCT but I think they're pretty similar.

You set output to one in cycle 63 and reset it in cycle 0 (=64), so the result is one pulse!

I would use autolimit for the cycle length, set output to 1 in cycle 0 (event0) and reset output
on match (event1) and use conflict resolution (not sure it's neccessary) to have precedence of reset over set.
That costs 3 matches and 2 events. Slightly more expensive, but should do what you want.

Marc

Re: PWM dutycycle of 0% using SCTtimers?

lpcware — Wed, 15 Jun 2016 19:22:59 GMT

Content originally posted in LPCWare by gstraka on Mon Apr 11 15:04:22 MST 2016

Quote: MarcVonWindscooting
I'm working with LPC800 SCT but I think they're pretty similar.

You set output to one in cycle 63 and reset it in cycle 0 (=64), so the result is one pulse!

I would use autolimit for the cycle length, set output to 1 in cycle 0 (event0) and reset output
on match (event1) and use conflict resolution (not sure it's neccessary) to have precedence of reset over set.
That costs 3 matches and 2 events. Slightly more expensive, but should do what you want.

Marc

Thanks Marc, I had the same question as OP and your answer helped me!

If this solution is more expensive, would it in theory be more efficient to take the original implementation and simply shut off the PWM for a 0% duty cycle?

Edit: Actually with the above solution, it's possible to get a 0% duty cycle but not a 100% duty cycle. It's basically reversing the problem, no?

Re: PWM dutycycle of 0% using SCTtimers?

lpcware — Wed, 15 Jun 2016 19:23:00 GMT

Content originally posted in LPCWare by renskessener on Tue Apr 12 04:22:36 MST 2016

From gstraka:
Edit: Actually with the above solution, it's possible to get a 0% duty cycle but not a 100% duty cycle. It's basically reversing the problem, no?

Yes, I agree. It reverses the problem. It is either 0% but not 100% or 100% and not 0%.

I figured out how to do it by using centre aligned PWM and a bidirectional counter. That works perfect.
Later I found It is also described in AN11538 (SCTimer/PWM cookbook), chapter 20.

So, for me the problem is solved.

Thanks for the replies.

Re: PWM dutycycle of 0% using SCTtimers?

lpcware — Wed, 15 Jun 2016 19:23:01 GMT

Content originally posted in LPCWare by gstraka on Tue Apr 12 07:56:20 MST 2016

Quote: renskessener
From gstraka:
Edit: Actually with the above solution, it's possible to get a 0% duty cycle but not a 100% duty cycle. It's basically reversing the problem, no?

Yes, I agree. It reverses the problem. It is either 0% but not 100% or 100% and not 0%.

I figured out how to do it by using centre aligned PWM and a bidirectional counter. That works perfect.
Later I found It is also described in AN11538 (SCTimer/PWM cookbook), chapter 20.

So, for me the problem is solved.

Thanks for the replies.

Thanks for the info...I've been looking at AN11538 but must have completely missed that chapter.

Re: PWM dutycycle of 0% using SCTtimers?

lpcware — Wed, 15 Jun 2016 19:23:02 GMT

Content originally posted in LPCWare by gstraka on Tue Apr 12 19:32:57 MST 2016

Maybe it's just me, but it seems like chapter 20 of AN11538 has some errors. For example:
[list]
[*]It says "MATCH[1].L = 0 results in 0% duty cycle (signal OFF)". I agree with this one.
[*]It says "MATCH[1].L = MATCH[0].L - 1 results in 100% duty cycle (signal ON)." This seems wrong, wouldn't it result in a near-0% duty cycle? To get 100% MATCH[1].L would have to equal MATCH[0].L.
[*]It says "0 < MATCH[1].L < MATCH[0].L - 1 results a 1 to 99% duty cycle." This seems correct except that the example implementation has it backwards. MATCH[1].L = 1 should result in a near-100% duty cycle while MATCH[1].L = MATCH[0].L - 1 should result in a near-0% duty cycle.
[/list]

Am I off base here?