LPC MicrocontrollersのトピックRe: penalty cycles for loosing 32 bit alignment

penalty cycles for loosing 32 bit alignment

lpcware — Wed, 15 Jun 2016 19:19:33 GMT

Content originally posted in LPCWare by khfreiberg on Fri Oct 26 13:07:01 MST 2012
Hi,
I am new on ARM, my last controller was a 16bit Fujitsu. I see that the controller has instructions to pick smaller data from accu, but I could not find anything about penalty cycles when PC or SP get unaligned (or if it is even possible).
Can somebody tell me how this controller behave? I have bad experiences with 16 bit controllers especially when SP got unaligned due to smaller stack data.
I would appreciate any help.

Re: penalty cycles for loosing 32 bit alignment

lpcware — Wed, 15 Jun 2016 19:19:33 GMT

Content originally posted in LPCWare by Pacman on Fri Nov 02 18:03:34 MST 2012
In my understanding, it's not possible at all, to misalign PC on the ARM.
Anyway, you would not need to 'misalign' at all, because there's plenty of memory available.

This is definitely something you'll want to read. Try reading it twice; I did (while you read it, you'll think "wow, cool" a few times):
http://simplemachines.it/doc/arm_inst.pdf

Re: penalty cycles for loosing 32 bit alignment

lpcware — Wed, 15 Jun 2016 19:19:34 GMT

Content originally posted in LPCWare by starblue on Mon Nov 05 04:28:59 MST 2012
> http://simplemachines.it/doc/arm_inst.pdf

That is from before the ARM Cortex era.

Better get the original documents about the ARM Cortex-M4/M0 from ARM.

E.g. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/index.html

Re: penalty cycles for loosing 32 bit alignment

lpcware — Wed, 15 Jun 2016 19:19:35 GMT

Content originally posted in LPCWare by khfreiberg on Mon Nov 05 11:53:30 MST 2012
Thanks,
that helps to justify my last minute decision to switch from Renesas to ARM. I like the 10 parallel register sets at Renesas for high speed interrupts, but I love the async dual core concept and the high speed USB. So I switched to ARM. Looks like the begin of a friendship ;-)).

Re: penalty cycles for loosing 32 bit alignment

lpcware — Wed, 15 Jun 2016 19:19:35 GMT

Content originally posted in LPCWare by Pacman on Thu Nov 08 04:19:30 MST 2012
I don't think you will regret. The 'A' in 'ARM' probably stands for 'Awesome'. ;)
You probably couldn't have made a better choice than NXP's ARM implementations.
Low cost, easy to use, a wide variety of chips, easily obtainable.
I recently switched from an 8-bit microcontroller to the LPC as well, the difference is indescribable.
In addition, my experience is that people in the LPC/NXP forums are very kind compared to some other forums. =)
BTW: If you need them, these are free tools for ARM microcontrollers: arm-gcc, OpenOCD - just google for them. They come in various distribution flavors.

Re: penalty cycles for loosing 32 bit alignment

lpcware — Wed, 15 Jun 2016 19:19:36 GMT

Content originally posted in LPCWare by MikeSimmonds on Mon Nov 12 06:58:32 MST 2012
Actually, the 'A' in ARM stands for 'Advanced'
as in Advanced RISC Machine.

Formerly, it was Acorn RISC Machine when the nucleous of the company was developing a processor for the "BBC Micro" in the UK (if anyone can remember that far back).

Re: penalty cycles for loosing 32 bit alignment

lpcware — Wed, 15 Jun 2016 19:19:36 GMT

Content originally posted in LPCWare by Pacman on Tue Nov 20 22:37:58 MST 2012
I do! :) I also saw an Acorn Archimedes once; just once (on CC93 in Göteborg).

Re: penalty cycles for loosing 32 bit alignment

lpcware — Wed, 15 Jun 2016 19:19:37 GMT

Content originally posted in LPCWare by khfreiberg on Wed Nov 21 10:01:09 MST 2012
Wow,
I grow up with Z80/8080. I have seen the 68000 GEM world outside the (ms)windows, but looks like I missed 'http://en.wikipedia.org/wiki/Acorn_Archimedes'. Probably not compatible ;-)))