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    <title>topic Re: SRAM error in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/SRAM-error/m-p/589502#M21941</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by mc on Fri Oct 24 09:12:27 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi yaofree,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Which device are you using? Full Part number? &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Can you also post schematic of your custom board? &lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 19:13:51 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T19:13:51Z</dc:date>
    <item>
      <title>SRAM error</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/SRAM-error/m-p/589501#M21940</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by yaofree on Wed Oct 22 01:32:59 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt; hi, I meet a SRAM problem.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; After writing a byte/word, I can read it ok . But After reading, the byte/word is disappeared and become a zero.&amp;nbsp; In other words, the writed word is disappeard and changed to zero after another read/write opperation.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I am very sad for 2 days for this. :(( .&amp;nbsp;&amp;nbsp; Can anyone&amp;nbsp; help me ?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;the SRAM chip is AS4C16M16S (256Mbit/16M * 16bit , 4Mword&amp;nbsp; * 16 bit * 4-bank)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;This is my part of&amp;nbsp; SDRAM_Init():&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_SCU-&amp;gt;EMCDELAYCLK = 0x2222 ; // 3.5 ns EMC clock delay&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//Also at higher clock rates you need to change EMCDELAYCLK (I have 0x0000 for up to 96MHz, 0x1111 for 97 to 129MHz and 0x2222 above that).&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;CONTROL = 0x00000001;// reset&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;CONFIG&amp;nbsp; = 0x00000000;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICCONFIG1&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0&amp;lt;&amp;lt;14 | 3&amp;lt;&amp;lt;9 | 1&amp;lt;&amp;lt;7; /* 256Mb, 16Mx16, 4 banks, row=13, column=9 */ // yao_todo&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;pclk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M4CORE);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICRASCAS1&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x00000303; /* 3 RAS, 3 CAS latency */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICREADCONFIG = 0x00000003; /* Command delayed strategy, using EMCCLKDELAY */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICRP&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = NS2CLK(pclk, 20);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICRAS&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = NS2CLK(pclk, 60);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICSREX&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = NS2CLK(pclk, 63);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICAPR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = NS2CLK(pclk, 63);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICDAL&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = NS2CLK(pclk, 63);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICWR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = NS2CLK(pclk, 20);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICRC&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = NS2CLK(pclk, 70);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICRFC&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = NS2CLK(pclk, 63);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICXSR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = NS2CLK(pclk, 63);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICRRD&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = NS2CLK(pclk, 14);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICMRD&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = NS2CLK(pclk, 20);//0x00000002;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; TIM_Waitus(100);&amp;nbsp;&amp;nbsp; /* wait 100ms */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICCONTROL&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x00000183; /* Issue NOP command */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;TIM_Waitus(200);&amp;nbsp;&amp;nbsp; /* wait 200ms */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICCONTROL&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x00000103; /* Issue PALL command */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICREFRESH&amp;nbsp;&amp;nbsp;&amp;nbsp; = /*2*/EMC_SDRAM_REFRESH(pclk,70); /* ( n * 16 ) -&amp;gt; 32 clock cycles */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;TIM_Waitus(200);&amp;nbsp;&amp;nbsp; /* wait 200ms */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;tmpclk = (uint64_t)15625 *(uint64_t)pclk/1000000000/16; // &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICREFRESH&amp;nbsp;&amp;nbsp;&amp;nbsp; = tmpclk;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICCONTROL&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x00000083; /* Issue MODE command */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;//Timing for 48/60/72MHZ Bus&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;temp = *((volatile uint32_t *)(SDRAM_ADDR_BASE | (2&amp;lt;&amp;lt;4| 3)&amp;lt;&amp;lt;11)); /* 4 burst, 3 CAS latency */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;temp = temp;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICCONTROL&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0;/* Issue NORMAL command */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC_EMC-&amp;gt;DYNAMICCONFIG1&amp;nbsp;&amp;nbsp;&amp;nbsp; |= 1&amp;lt;&amp;lt;19;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:13:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/SRAM-error/m-p/589501#M21940</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:13:50Z</dc:date>
    </item>
    <item>
      <title>Re: SRAM error</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/SRAM-error/m-p/589502#M21941</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by mc on Fri Oct 24 09:12:27 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi yaofree,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Which device are you using? Full Part number? &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Can you also post schematic of your custom board? &lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:13:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/SRAM-error/m-p/589502#M21941</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:13:51Z</dc:date>
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