LPC MicrocontrollersのトピックRe: LPC1788 Ethernet corupted or missing tx packets

LPC1788 Ethernet corupted or missing tx packets

lpcware — Wed, 15 Jun 2016 17:29:14 GMT

Content originally posted in LPCWare by X-log on Fri Nov 29 10:54:25 MST 2013
HW: Embedded Artist LPC1788 dev board @ 120 MHz (LAN8720 over RMII)

SW: freeRTOS + lwip + zero-copy driver
Emac DMA descriptors are in peripheral RAM (0x20000000). Lwip memory pools and freertos heap are in external RAM.

Task: transmitting data over TCP at ~4mbps.

My problem is that some packets have a corrupt single lower nibble. Sometimes this also happens then packet is retransmitted, but usually fast retransmit succeeds (data is not modified/copied between retransmits, checksum is for correct data. Maybe emac DMA reads incorrectly from external ram?)
Also, some tx packets are missing entirely.

I’m also attaching test software project.

Any help would be appreciated.

Original Attachment has been moved to: lpc1788EthTest.rar

Re: LPC1788 Ethernet corupted or missing tx packets

lpcware — Wed, 15 Jun 2016 17:29:15 GMT

Content originally posted in LPCWare by artshadow on Mon Dec 30 23:54:15 MST 2013
Hi,
I encountered a similar problem on my project.
I am trying to run both lwIP and emWin under FreeRTOS, and both of them are working fine on their own, however if I enable power to the LCD controller, some tx packets sent out by lwip are missing entirely. Both lwIP memory pools and emWin buffers are located in external RAM. It seems like some sort of conflict accessing the external RAM by the ethernet and LCD controller.
Tried changing the AHB Matrix priorities, but did not help.
Any other ideas?

Re: LPC1788 Ethernet corupted or missing tx packets

lpcware — Wed, 15 Jun 2016 17:29:16 GMT

Content originally posted in LPCWare by artshadow on Sun Jan 05 17:54:34 MST 2014
I managed to solve my problem. I was getting TX underrun errors for most of the packets because the LCD controller was using up all my bandwith to the external memory.
I increased the bandwith by increasing the EMC clock rate from 60MHz to 105MHz and tweaked SDRAM timings, while checking SDRAM performance and read/write errors.
Then I limited the LCD controller bandwith by reducing the refresh rate (pixel clock).