LPC MicrocontrollersのトピックHow many I2S could be possible using SGPIOs in LPC4357 ?

How many I2S could be possible using SGPIOs in LPC4357 ?

lpcware — Wed, 15 Jun 2016 19:11:24 GMT

Content originally posted in LPCWare by kiyoong on Wed Sep 02 23:00:18 MST 2015
HI NXP team,

It's a beautiful weather after hot summer day !!

How many I2S could be possible using SGPIOs in LPC4357 ?

I saw the user manual and found out that LPC43xx has 2 I2S and 16 SGPIO pins.
In a previous question, I knew that NXP team changed SGPIO into 2 I2S channels and made 7.1 audio output.
(including 2 I2S..) therefore, 4 I2S would be possible.

however, LPC43xx has 16 SGPIO pins and someone mentioned that If clock and etc pins shared, more I2S would be supported.

Please, Answer my simple question.
How many I2S could be possible using SGPIOs in LPC4357 ?

thank you.

Re: How many I2S could be possible using SGPIOs in LPC4357 ?

lpcware — Wed, 15 Jun 2016 19:11:25 GMT

Content originally posted in LPCWare by bavarian on Mon Sep 14 05:30:34 MST 2015
It depends on your needs of the I2S interfaces.
Let's assume you need in/out on all I2S interfaces, a common clock and a common frame sync:

1 clock
1 frame sync
7 x in/out
-----------------
16 pins

This is it for the pins. If you can handle this in software from the SGPIO point of view is another question. You need to serve 7 channels in time. If you have only output, then of course things become much easier. You need to update 7 output registers regularly with stereo audio data either using DMA and/or the processor.

There is a software example using 4 SGPIO pins for a four channel I2S TX. Look in the folder \lpc43xx\Examples\SGPIO in this software package:

https://www.lpcware.com/content/nxpfile/lpc4350apdlzip

Doing for example 6 channels instead of these 4 shouldn't be a problem.

Regards,
NXP Support Team

Re: How many I2S could be possible using SGPIOs in LPC4357 ?

lpcware — Wed, 15 Jun 2016 19:11:25 GMT

Content originally posted in LPCWare by kiyoong on Mon Sep 14 18:13:03 MST 2015
Dear NXP Support Team,

Thank you for sharing SGPIO example.

Q1) 2 slice buffer would be necessary for 1 channel of I2S ?

In this example, 4SGPIO pins was used for a four channel I2S TX. However, each I2S channel needed 2 slice buffer of SGPIO. refer to the source code below.
--------
LPC_SGPIO->SGPIO_MUX_CFG[1] =
LPC_SGPIO->SGPIO_MUX_CFG[12] = CONCAT_ENABLE | SLICE_2;

LPC_SGPIO->POS[1] =
LPC_SGPIO->POS[12] = ((0x020*2 - 1) << 8) | (0x020*2 - 1);

LPC_SGPIO->OUT_MUX_CFG[9] = 0;// output the data bit on SGPIO9
-------------
Does it mean that 2 slice buffer would be necessary for 1 channel of I2S ?
If then, we could make 7 output channels with 16 slice buffers. Am I right ?

Q2) Could it be possible to implement Tx and Rx, and Use it at the same time ?
Actually, we are supposed to build TX and RX channels.
In this case, I think ~~
1 frame sync,
1 clock,
3 TX channels (with 2 slice buffers each )
--- totally 8 pins and slice buffers for TX. Of course RX part will equal to TX.
therefore, 3 TX and 3 RX are the maximum count of SGPIO.

Is My understanding correct ? Is it possible ?

Sorry for bothering with too many questions.