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    <title>topic LPCOpen2.12 sdmmc / massstorage performance bug in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPCOpen2-12-sdmmc-massstorage-performance-bug/m-p/586848#M21504</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by mengxp on Sun Jun 12 23:01:19 MST 2016&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;void Chip_SDIF_SetClock(LPC_SDMMC_T *pSDMMC, uint32_t clk_rate, uint32_t speed)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;/* compute SD/MMC clock dividers */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;uint32_t div;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;div = ((clk_rate / speed) + 2) &amp;gt;&amp;gt; 1;&amp;nbsp;&amp;nbsp; &amp;lt;&amp;lt;&amp;lt; div here compute wrong&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;when I set speed=51MHz, div result is = 3.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;so SD clock acturally be set at 204MHz / (2*3) = 34MHz. &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;SD bandwidth = 34M * 4 / 8 = 17MB/s&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;and test result is:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;card_init&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clk_rate: 204000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;speed: 20000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;div: 6&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clk_rate: 204000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;speed: 51000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;div: 3&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;speed: 51000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clk_rate: 0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Speed testing...&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Read Speed: 14075 KB/s&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I correct above bug code&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;div = (clk_rate / speed) &amp;gt;&amp;gt; 1;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;so div will be set to 2 correctly, SD clock will be set at 204MHz / 2*2 = 51MHz&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;SD bandwidth = 51M * 4 / 8 = 25.5MB/s&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;and test result is&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;card_init&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clk_rate: 204000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;speed: 20000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;div: 5&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clk_rate: 204000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;speed: 51000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;div: 2&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;speed: 51000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clk_rate: 0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Speed testing...&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Read Speed: 19621 KB/s&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;see? that is a big improve!&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;And why the Mass Storoge example run at a bad performance about:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Read: 7MB/s&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Bacause this example use a synchronous SD Read/Write&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;So read/write performance will be cut about a half.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Use double buffer and asynchronous SD read/write will do better performance&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 20:27:07 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T20:27:07Z</dc:date>
    <item>
      <title>LPCOpen2.12 sdmmc / massstorage performance bug</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPCOpen2-12-sdmmc-massstorage-performance-bug/m-p/586848#M21504</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by mengxp on Sun Jun 12 23:01:19 MST 2016&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;void Chip_SDIF_SetClock(LPC_SDMMC_T *pSDMMC, uint32_t clk_rate, uint32_t speed)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;/* compute SD/MMC clock dividers */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;uint32_t div;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;div = ((clk_rate / speed) + 2) &amp;gt;&amp;gt; 1;&amp;nbsp;&amp;nbsp; &amp;lt;&amp;lt;&amp;lt; div here compute wrong&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;when I set speed=51MHz, div result is = 3.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;so SD clock acturally be set at 204MHz / (2*3) = 34MHz. &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;SD bandwidth = 34M * 4 / 8 = 17MB/s&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;and test result is:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;card_init&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clk_rate: 204000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;speed: 20000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;div: 6&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clk_rate: 204000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;speed: 51000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;div: 3&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;speed: 51000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clk_rate: 0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Speed testing...&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Read Speed: 14075 KB/s&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I correct above bug code&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;div = (clk_rate / speed) &amp;gt;&amp;gt; 1;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;so div will be set to 2 correctly, SD clock will be set at 204MHz / 2*2 = 51MHz&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;SD bandwidth = 51M * 4 / 8 = 25.5MB/s&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;and test result is&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;card_init&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clk_rate: 204000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;speed: 20000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;div: 5&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clk_rate: 204000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;speed: 51000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;div: 2&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;speed: 51000000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clk_rate: 0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Speed testing...&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Read Speed: 19621 KB/s&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;see? that is a big improve!&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;And why the Mass Storoge example run at a bad performance about:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Read: 7MB/s&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Bacause this example use a synchronous SD Read/Write&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;So read/write performance will be cut about a half.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Use double buffer and asynchronous SD read/write will do better performance&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 20:27:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPCOpen2-12-sdmmc-massstorage-performance-bug/m-p/586848#M21504</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T20:27:07Z</dc:date>
    </item>
    <item>
      <title>Re: LPCOpen2.12 sdmmc / massstorage performance bug</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPCOpen2-12-sdmmc-massstorage-performance-bug/m-p/586849#M21505</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by NXP_Support on Mon Jun 13 08:42:00 MST 2016&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi Mengxp,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Great work!&amp;nbsp; Thank you for tracking this down and providing your results!&amp;nbsp; We are reviewing your suggested fix across all clock ranges for updating the code base.&amp;nbsp; The issue and your fix have been logged in our internal LPCOpen system and will be fixed in our updates.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Best regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;-NXP Support&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 20:27:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPCOpen2-12-sdmmc-massstorage-performance-bug/m-p/586849#M21505</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T20:27:08Z</dc:date>
    </item>
    <item>
      <title>Re: LPCOpen2.12 sdmmc / massstorage performance bug</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPCOpen2-12-sdmmc-massstorage-performance-bug/m-p/586850#M21506</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;bump&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 19 Jun 2016 01:13:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPCOpen2-12-sdmmc-massstorage-performance-bug/m-p/586850#M21506</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-19T01:13:00Z</dc:date>
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