LPC MicrocontrollersのトピックRe: Request From NXP microcontroller Designer/Planer team : "Application processor/Fpga multi DSP " repalcement design

Request From NXP microcontroller Designer/Planer team : "Application processor/Fpga multi DSP " repalcement design

lpcware — Wed, 15 Jun 2016 19:14:10 GMT

Content originally posted in LPCWare by ganigangi on Fri Oct 25 04:54:05 MST 2013
Hi,

I have already worked on LPC1768

and my program codes was grown till all 512KB of flash was filled
in between because of small 32k+32k bytes of SRAM I was challenging for each code pieces addition
and gradually I encountered the speed limitation ( 100MHZ )

then I planned to migrate to LPC1788 , but it has the same limitation ( 96KB RAM , 120MHZ speed )

I was around to select CM4 such as LPC43xx , but the limitations are the same

flash = 512KB , 1024KB
RAM = 136KB

for my future developments I need

- more than or equal to 2048 KB of FLASH code memory ( 3072MB+ is the best for me )
- more than 256 KB of RAM memory ( 512KB+ is the best for me )

NXP forces me to use flashless CM4 that has more RAM ( 168KB , 200KB , 264KB )
but it should be add external memory and more pcb area

I am confused!

I think there will be a fast growing demand for massive computing power and more larger memory in near future

it is good idea to :

- adding external memory on the top of chip ( 256MB , 512MB , 1024MB SDRAM DDRn )

- increasing core speed to 600MHZ ... 1200MHZ

- adding more cores and dedicated RAM for each core (16...256 cores , 32kB for each ) ( from massive FPGA world )

- adding more I/O pins ( 100 ... 1500 pins ) ( from massive FPGA world )

- adding LVDS IO transeciver logic ( from massive FPGA world )

- increasing ethernet speed to 1000

======================================================================

these devices will be massively used in automotive ( 1 ... 5 parts per NEW CAR ) on 2015 and next
( where I and my team and competitors are hardly working on projects that based on massive FPGA but expensive )

and for PLC for Industrial

and on IMAGING for MRI_ULTRASOUND

and for military or industrial RADAR

======================================================================

..........

and it would be great that the chip designers to add hardware's to handle RTOS operations and remove
the " time consuming software overhead" of it

as :
- adding a huge amount of banked registers ( eg: 64 banks of 64word(4bytes) register bank for 64 individual tasks = 64*64*4= 16KBYTES )
( removing the PUSH POP or save and restore on each task

- dedicated RTOS tik timer and a "time plan file" ( a 64 * 2bytes register to define each task "time share" ) + 64*1bytes for priority

- and a connection matrix bus between cores to improve access speed

- and more functional DMA controller to remove any overhead from CPU

it is a large design ......
but the first vendor that will generate this device
will have the huge market share of $10Billion yearly

======================================================================================================
[color=#093]
really I need ALL_IN_ONE solution indeed[/color]

think it: why should we ( designers ) have to gather too many parts on PCB and route and check and verify and redesign and repeat....

why there isn't a enough [color=#63f]" total solution in small packages "[/color] ( like DS1643 RTC_NVRAM ) or ( AD_POWER MODULE )

to help us to jump to final design

hmmmm???

======================================================================================================

[color=#33f]I hope someone from semiconductor vendors , to monitor this forum and
provide these solutions for all customer around the world[/color]

======================================================================================================
[color=#33c]
it should be named "Field Programmable Core Array" = FPCA or something[/color]

======================================================================================================

Re: Request From NXP microcontroller Designer/Planer team : "Application processor/Fpga multi DSP " repalcement design

lpcware — Wed, 15 Jun 2016 19:14:11 GMT

Content originally posted in LPCWare by rocketdawg on Fri Oct 25 06:47:33 MST 2013
there is such a part.

it's called an ARM A8.

Re: Request From NXP microcontroller Designer/Planer team : "Application processor/Fpga multi DSP " repalcement design

lpcware — Wed, 15 Jun 2016 19:14:11 GMT

Content originally posted in LPCWare by ganigangi on Fri Oct 25 10:31:56 MST 2013
hi,

do you mean ARM CORTEX-A8 ?

it is an application processor and the cores was 1,2,4 without professional DSP

TI has already built ARM CORTEX-A15(2,4 cores) beside 4,8 DSP core ( this is nearest one for my plans )

66AK2H12/06
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

[color=#33f]Eight (66AK2H12) or Four (66AK2H06)
TMS320C66x™ DSP Core Subsystems (C66x
CorePacs), Each With
– Up to 1.2 GHz C66x Fixed/Floating-Point DSP
Cores[/color]
› 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
› 19.2 GFlops/Core for Floating Point @ 1.2 GHz
– Memory
› 32K Byte L1P Per CorePac
› 32K Byte L1D Per CorePac
› 1024K Byte Local L2 Per CorePac

[color=#063]• ARM® Cortex™-A15 MPCore™ Processors Containing
Four (66AK2H12) or Two (66AK2H06) ARM
Cortex-A15 Cores
– Up to 1.4-GHz Cortex-A15 Processor Core Speed[/color]
– 4MB L2 Cache Memory Shared by All ARM
CorePacs
– Full Implementation of ARMv7-A Architecture
Instruction Set
– 32KB L1 Instruction Cache and Data Cache per
Cortex-A15 Processor Core
– AMBA 4.0 AXI Coherency Extension (ACE) Master
Port, Connected to MSMC for Low Latency Access
to Shared MSMC SRAM
• Multicore Shared Memory Controller (MSMC)
– 6 MB MSM SRAM Memory Shared by DSP CorePacs
and ARM CorePac
– Memory Protection Unit for Both MSM SRAM and
DDR3_EMIF
• Multicore Navigator
– 16k Multi-Purpose Hardware Queues with Queue
Manager
– Packet-Based DMA for Zero-Overhead Transfers

Re: Request From NXP microcontroller Designer/Planer team : "Application processor/Fpga multi DSP " repalcement design

lpcware — Wed, 15 Jun 2016 19:14:12 GMT

Content originally posted in LPCWare by rocketdawg on Fri Oct 25 11:08:21 MST 2013
You have read the data sheet so you do know that the LPC43xx has an external memory bus for SRAM, ROM, NOR flash, and SDRAM devices.

Or use the A15
you cannot expect a Cortex M3/M4 (~$10) to compete with a Cortex A15 (~$50 + DDR3 cost + FLASH cost), probably $100 total hardware cost.
now add markup and profit.
now add 1 to 5 in each vehicle?
This had better be good if it raises the cost of the vehicle by several thousand dollars.

Re: Request From NXP microcontroller Designer/Planer team : "Application processor/Fpga multi DSP " repalcement design

lpcware — Wed, 15 Jun 2016 19:14:13 GMT

Content originally posted in LPCWare by wmues on Sat Oct 26 00:40:06 MST 2013
It _is_ possible to build "bigger" systems with the LPC 178x.
I am using a SDRAM as code and data memory. In the internal flash is a bootloader, and
the code is stored in an inexpensive serial flash. Some code is copied into internal RAM for speed.
And not to forget: the STACK is in internal RAM too...

Code size is 4 MBytes, Data Size 2 MBytes. Very fine machine.

I have also used AM335x from TI, and beside the very limited quality of the device drivers (a fact that is common these days), this is a fine chip and very usable for many designs, and the total system costs are low.

regards
Wolfgang

Re: Request From NXP microcontroller Designer/Planer team : "Application processor/Fpga multi DSP " repalcement design

lpcware — Wed, 15 Jun 2016 19:14:14 GMT

Content originally posted in LPCWare by ganigangi on Sat Oct 26 02:40:53 MST 2013

Quote: rocketdawg
You have read the data sheet so you do know that the LPC43xx has an external memory bus for SRAM, ROM, NOR flash, and SDRAM devices.

Or use the A15
you cannot expect a Cortex M3/M4 (~$10) to compete with a Cortex A15 (~$50 + DDR3 cost + FLASH cost), probably $100 total hardware cost.
now add markup and profit.
now add 1 to 5 in each vehicle?
This had better be good if it raises the cost of the vehicle by several thousand dollars.

Hi,

we all know the features of LPC43xx , and for many applications , these features and peripherals are very good and enough.

we all know the price levels of these microcontrollers/processors chips families . ( also the application section of these devices )

but in the progress roadmap of IC Design technologies , we can imagine and expect all prementioned requests.

( Integration of external memories on the top of CPU chip , then many of bus problems will not be the headache )
( making some modules for / power/analog in/analog out/digital in/digital out/ ethernet pack/ display pack/ ... such as puzzle parts/ )
( massive processing capability for current and future applications )

know for many advanced applications that we need very expensive FPGA chips,
for production and marketing of them, at the current time, there is not a direct inexpensive solutions.

so, someone from vendors should step ahead and solve this.

regards

ganigangi