topic LPC1788 DAC BIAS in LPC Microcontrollers

LPC1788 DAC BIAS

lpcware — Wed, 15 Jun 2016 17:26:56 GMT

Content originally posted in LPCWare by wella-tabor on Fri Apr 26 01:57:14 MST 2013

Hello, does anyone know what is DAC BIAS bit good for?

The user manual v2.1 states:

page 828 - Selectable speed vs. power

page 830 -

bit 6 BIAS Settling time

The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet.

0 The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz.

1 The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz.

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It seems that if I enable the BIAS I will get only worse functionality of the DAC, nothing more. Of course there is not any graph in the final data sheet.

Best Martin

Re: LPC1788 DAC BIAS

lpcware — Wed, 15 Jun 2016 17:26:57 GMT

Content originally posted in LPCWare by Wouter on Fri Apr 26 02:47:00 MST 2013

Hi Martin,

>>It seems that if I enable the BIAS I will get only worse functionality of the DAC, nothing more

Depends on how you look at it! If 400KHz of bandwidth (with cap load on DAC_OUT < 100pF) is enough for your application, you can set this bit and benefit from lower power consumption.

So, basically this bit let you make a trade-off between bandwidth and power consumption.

Regards,

Wouter

Re: LPC1788 DAC BIAS

lpcware — Wed, 15 Jun 2016 17:26:58 GMT

Content originally posted in LPCWare by wella-tabor on Fri Apr 26 02:59:12 MST 2013
Hi,

that's make sense. Thank You very much for clarification.

Martin