topic Re: Bugs in AN11538? in LPC Microcontrollers

Bugs in AN11538?

lpcware — Wed, 15 Jun 2016 17:06:38 GMT

Content originally posted in LPCWare by 1234567890 on Wed Oct 29 13:24:07 MST 2014
As a new proud owner of a LPCXPpresso LPC1549 with SCT (which I've never heard before) I started to read the related section in the UM. After a few sentences I was scared about this peripheral and stopped reading. I decided to look for a special article and found AN11538.
I just flew over the example code and was scared again: Is this peripheral really that complicated or are there a few bugs in the AN? I haven't checked any registers in the UM, but

Fig 2:
LPC_SCT->MATCHREL[0].U = SystemCoreClock/100;// match 0 @ 100 Hz = 10 msec
=> all the other examples have -1 behind

Fig 4:
LPC_SCT->OUT[0].SET = (1 << 0); // event 0 will set SCT_OUT0
LPC_SCT->OUT[0].CLR = (1 << 1); // event 0 will clear SCT_OUT0
=> all the other examples have the same bits in SET and CLR

Fig 6:
LPC_SCT->EVENT[0].STATE = 0xFFFF; // event 0 happens in all state
=> all the other examples have 0xFFFFFFFF for all states

and so on. So are this bugs or is it really not logical (at least for me at the first and veeeery quick view)?

Re: Bugs in AN11538?

lpcware — Wed, 15 Jun 2016 17:06:39 GMT

Content originally posted in LPCWare by NXP_Paul on Fri Oct 31 06:14:23 MST 2014
Thank you for your feedback.
Fig. 2: I believe you are correct, and I will notify our documentation group to have this changed.
Fig. 4: Not sure what you mean by this comment, since the AN looks correct:
LPC_SCT->OUT[0].CLR = (1 << 1); // event 1 will clear SCT_OUT0
Fig 6: It depends which device you are using. Some devices only have two states (LPC81x), the LPC11U6x has 8 states, while others like the LPC15xx have 16 states, so 0xFFFF would be correct for this device. Using 0xFFFFFFFF for any of the devices would work fine.

Paul

Re: Bugs in AN11538?

lpcware — Wed, 15 Jun 2016 17:06:40 GMT

Content originally posted in LPCWare by 1234567890 on Sat Nov 01 06:21:03 MST 2014

Quote: NXP_Paul

Fig. 4: Not sure what you mean by this comment, since the AN looks correct:
LPC_SCT->OUT[0].CLR = (1 << 1); // event 1 will clear SCT_OUT0
Paul

Well, I assumed that, if there is a *.SET and a *.CLR command, that the same bit position is used. Only SET and CLR differ; using SET will set the bit and CLR will clear the bit.
But now I see that there are different events and so the example differs from e.g. Fig 8, where the conflict resolution register is used. So it seems to be a complete different story and the the functionality of this register is not as assumed (by me).

Obviously there is no alternative to read the relating chapter in the UM (surprise, surprise)...