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    <title>LPC Microcontrollers中的主题 Cannot correctly determine clock rates for UART0 /SSP1 APB clocks</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Cannot-correctly-determine-clock-rates-for-UART0-SSP1-APB-clocks/m-p/583061#M20803</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by cfgardiner on Wed Jan 07 09:40:05 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I am developing a customer project based on the LPC1837. Using the lpcopen functions, I cannot determine the clockrate of the APB clocks driving the UART0 or SSP1 peripherals:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I have tried:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//&amp;nbsp;&amp;nbsp; uart0Rate&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = Chip_Clock_GetRate(CLK_APB0_UART0);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; uart0Rate&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = Chip_Clock_GetBaseClocktHz(CLK_BASE_UART0);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; ssp1Rate&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = Chip_Clock_GetRate(CLK_APB2_SSP1);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The value return is always zero.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I have the following setup which derives a 48 MHz base clock from the USB0 PLL:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 2);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; Chip_Clock_SetDivider(CLK_IDIV_B, CLKIN_IDIVA, 5);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; Chip_Clock_SetDivider(CLK_IDIV_C, CLKIN_IDIVA, 5);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; Chip_Clock_SetBaseClock(CLK_BASE_UART0, CLKIN_IDIVB, true, false);&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; Chip_Clock_SetBaseClock(CLK_BASE_UART1, CLKIN_IDIVB, true, false);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; Chip_Clock_SetBaseClock(CLK_BASE_SSP1, CLKIN_IDIVC, true, false);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; Chip_Clock_SetBaseClock(CLK_BASE_OUT, CLKIN_IDIVB, true, false);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I have verified that this works with a scope so it seems purely be an lpcopen software issue. If I feed the output from DIVA, DIVB or DIVC to CLKOUT[0] I measure the expected clock rates.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Charles&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 20:25:29 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T20:25:29Z</dc:date>
    <item>
      <title>Cannot correctly determine clock rates for UART0 /SSP1 APB clocks</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Cannot-correctly-determine-clock-rates-for-UART0-SSP1-APB-clocks/m-p/583061#M20803</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by cfgardiner on Wed Jan 07 09:40:05 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I am developing a customer project based on the LPC1837. Using the lpcopen functions, I cannot determine the clockrate of the APB clocks driving the UART0 or SSP1 peripherals:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I have tried:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//&amp;nbsp;&amp;nbsp; uart0Rate&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = Chip_Clock_GetRate(CLK_APB0_UART0);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; uart0Rate&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = Chip_Clock_GetBaseClocktHz(CLK_BASE_UART0);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; ssp1Rate&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = Chip_Clock_GetRate(CLK_APB2_SSP1);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The value return is always zero.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I have the following setup which derives a 48 MHz base clock from the USB0 PLL:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 2);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; Chip_Clock_SetDivider(CLK_IDIV_B, CLKIN_IDIVA, 5);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; Chip_Clock_SetDivider(CLK_IDIV_C, CLKIN_IDIVA, 5);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; Chip_Clock_SetBaseClock(CLK_BASE_UART0, CLKIN_IDIVB, true, false);&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; Chip_Clock_SetBaseClock(CLK_BASE_UART1, CLKIN_IDIVB, true, false);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; Chip_Clock_SetBaseClock(CLK_BASE_SSP1, CLKIN_IDIVC, true, false);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; Chip_Clock_SetBaseClock(CLK_BASE_OUT, CLKIN_IDIVB, true, false);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I have verified that this works with a scope so it seems purely be an lpcopen software issue. If I feed the output from DIVA, DIVB or DIVC to CLKOUT[0] I measure the expected clock rates.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Charles&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 20:25:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Cannot-correctly-determine-clock-rates-for-UART0-SSP1-APB-clocks/m-p/583061#M20803</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T20:25:29Z</dc:date>
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