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    <title>topic Re: SSP1 ISR triggered with MIS register = 0x00000000 and RIS = 0x00000008 in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/SSP1-ISR-triggered-with-MIS-register-0x00000000-and-RIS/m-p/582799#M20749</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by jgorsk on Wed Sep 19 13:03:33 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;The problem is solved. Last line in SSP1_IRQHandler was clearing TXIM bit.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;In assembly code it was followed only by 'BX&amp;nbsp; lr' command. If any other C code&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;line is inserted after clearing TXIM bit, SSP1 interrupt status bits are working fine&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;and there are no 'false' SSP1 interrupts.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Before TXIM bit was actually cleared another SSP1 ISR was triggered. ARM architecture &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;is new to me so I'm not exactly sure why it works that way. Is it becasue of the pipeline&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;architecture of the CPU or the actual writes to the registers are delayed?&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 19:05:42 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T19:05:42Z</dc:date>
    <item>
      <title>SSP1 ISR triggered with MIS register = 0x00000000 and RIS = 0x00000008</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/SSP1-ISR-triggered-with-MIS-register-0x00000000-and-RIS/m-p/582798#M20748</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by jgorsk on Wed Sep 19 06:05:57 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm using SSP1 on the LPC4337 in SPI mode. Sometimes (not always) SSP1 interrupt is triggered &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;with MIS = 0x00 and RIS&amp;nbsp; = 0x08. IMSC at that time&amp;nbsp; is 0x00.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm sending a train of words over SPI by first preparing a buffer and setting TXIM bit &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;in IMSC register from my main program. Then a SSP1 ISR is triggered which writes &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;the word to be sent to SSP1 data register and then clears TXIM disabling SSP1 interrupt. &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;SSP1 generates CS signal automatically. When SPI transfer is finished the CS signal generates &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;a pin&amp;nbsp; interrupt or its rising edge. The pin interrupt ISR generates a few other signals &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;which latch data in the slave SPI devices. It then sets TXIM to re-enable SSP1 interrupt &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;and the cycle is repeated.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;When the SSP1 ISR is triggered and there is no more data to be sent in my buffer&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;the SSP1 ISR will just clear TXIM bit.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I can't find a detailed description of how the SSP1 interrupt signals and interrupt&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;masking work.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;There may be something wrong with my program but regardless of that how can an ISR&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;be triggered with Masked Interrupt Status register being 0x00?&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:05:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/SSP1-ISR-triggered-with-MIS-register-0x00000000-and-RIS/m-p/582798#M20748</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:05:41Z</dc:date>
    </item>
    <item>
      <title>Re: SSP1 ISR triggered with MIS register = 0x00000000 and RIS = 0x00000008</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/SSP1-ISR-triggered-with-MIS-register-0x00000000-and-RIS/m-p/582799#M20749</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by jgorsk on Wed Sep 19 13:03:33 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;The problem is solved. Last line in SSP1_IRQHandler was clearing TXIM bit.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;In assembly code it was followed only by 'BX&amp;nbsp; lr' command. If any other C code&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;line is inserted after clearing TXIM bit, SSP1 interrupt status bits are working fine&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;and there are no 'false' SSP1 interrupts.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Before TXIM bit was actually cleared another SSP1 ISR was triggered. ARM architecture &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;is new to me so I'm not exactly sure why it works that way. Is it becasue of the pipeline&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;architecture of the CPU or the actual writes to the registers are delayed?&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:05:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/SSP1-ISR-triggered-with-MIS-register-0x00000000-and-RIS/m-p/582799#M20749</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:05:42Z</dc:date>
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