topic Re: LPC4370 ACDHS speed in LPC Microcontrollers

LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:02 GMT

Content originally posted in LPCWare by dmorse on Fri Jan 24 09:24:01 MST 2014
How do I set up the BASE_M4_CLK or the AHB clocks for high speed ADC?

How do I verify the BASE_ADCHS_CLK is running (204Mhz ) fast enough for 80Msample?

I have the ADCHS running but the max I can sample is 2Khz.

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:02 GMT

Content originally posted in LPCWare by nmz787 on Fri Jan 24 14:25:24 MST 2014
In the ADCHS example there's a few lines I noticed (though I haven't had much time to work with these boards yet):

/* HSADC clock rate used for sampling */
#define HSADC_CLOCK_RATE (80 * 1000000)

and also

/* Periodic sample rate in Hz */
#define SAMPLERATE (20)

I was playing with different values for

SAMPLERATE

since the LED blinks when a sample is taken (I believe that's how it was), and I could see different values would make the LED change blink rate... so I think that's what I'd try first.

Or maybe you're starting with the LabTool code?

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:03 GMT

Content originally posted in LPCWare by dmorse on Fri Jan 24 16:52:10 MST 2014
The SAMPLERATE is used to set a timer to send a software trigger to the ADCHS.

WhenI view the fADC clock it is at 12Mhz.
freq = Chip_Clock_GetRate(CLK_ADCHS);

I single step through the code that sets up the clocking but it start to do the right thing. It hard to trace with the EXPResso IDE.

No sure why but it looks like it can't find a free divider. The code is very hard to follow.

I don't have the LabTool code,( Where can I find it?) just using the 'periph_hsadc.c' example.

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:04 GMT

Content originally posted in LPCWare by nmz787 on Sun Jan 26 15:38:40 MST 2014
What do you have

HSADC_CLOCK_RATE

defined as?

LabTool code is available here (they also have the compiled firmware which you can load with LPC LInk2 Config Tool), it's a Keil MDK project, but the free/lite version of Keil MDK won't link the compiled code, as it's greater than the 32kb limit the lite version provides. I haven't had time, but I plan to get the LabTool code running in LPCXpresso next.

Source:
https://github.com/embeddedartists/labtool

Binaries (firmware and GUI application):
http://www.embeddedartists.com/products/app/labtool.php

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:04 GMT

Content originally posted in LPCWare by dmorse on Mon Jan 27 06:36:36 MST 2014
I have it set to:

* HSADC clock rate used for sampling */
#define HSADC_CLOCK_RATE (80 * 1000000)

This shows the timer1 clock is 204Mhz:

//Chip_Clock_GetRate(CLK_MX_TIMER1)
  int freq = Chip_Clock_GetRate(CLK_MX_TIMER1);

This shows the fADC is 12Mhz:

//Chip_Clock_GetRate(CLK_ADCHS)
  freq = Chip_Clock_GetRate(CLK_ADCHS);

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:05 GMT

Content originally posted in LPCWare by wellsk on Mon Jan 27 10:53:00 MST 2014
The periph_hsadc example needs to work on multiple boards and those boards all have different clock setups. The example, with it's complex clock setup, tries to work on all those boards by determing at run-time what the clock tree looks like.

But in reality, the HSADC clock structure is very simple and can be setup by directly setting the HSADC base clock with this one function:

Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, <SOME CLOCK INPUT>, true, false);

You can attach the HSADC base clock to any of the following clock inputs:

/**
 * @brief CGU clock input list
 * These are possible input clocks for the CGU and can come
 * from both external (crystal) and internal (PLL) sources. These
 * clock inputs can be routed to the base clocks (@ref CHIP_CGU_BASE_CLK_T).
 */
typedef enum CHIP_CGU_CLKIN {
CLKIN_32K,/*!< External 32KHz input */
CLKIN_IRC,/*!< Internal IRC (12MHz) input */
CLKIN_ENET_RX,/*!< External ENET_RX pin input */
CLKIN_ENET_TX,/*!< External ENET_TX pin input */
CLKIN_CLKIN,/*!< External GPCLKIN pin input */
CLKIN_RESERVED1,
CLKIN_CRYSTAL,/*!< External (main) crystal pin input */
CLKIN_USBPLL,/*!< Internal USB PLL input */
CLKIN_AUDIOPLL,/*!< Internal Audio PLL input */
CLKIN_MAINPLL,/*!< Internal Main PLL input */
CLKIN_RESERVED2,
CLKIN_RESERVED3,
CLKIN_IDIVA,/*!< Internal divider A input */
CLKIN_IDIVB,/*!< Internal divider B input */
CLKIN_IDIVC,/*!< Internal divider C input */
CLKIN_IDIVD,/*!< Internal divider D input */
CLKIN_IDIVE,/*!< Internal divider E input */
CLKINPUT_PD/*!< External 32KHz input */
} CHIP_CGU_CLKIN_T;

Quote:

This shows the fADC is 12Mhz:

//Chip_Clock_GetRate(CLK_ADCHS)
freq = Chip_Clock_GetRate(CLK_ADCHS);

If you are getting 12Mhz from the HSADC peripheral clock read functions, your base clock is likely the 12MHz IRC or external oscillator.

You will have to work a little bit to get an exact 80Mhz to the HSADC. The easiest way to do it would be to setup the audio PLL to 80MHz and use it as HSADC base clock. This would require you to use the tool at http://www.lpcware.com/content/nxpfile/audio-pll-settings-calculation-tool to get the audio PLL coefficients with the audio PLL setup functions.

Here are some other possibilities that won't give you an exact 80MHz: There are 5 possible dividers in the 18xx/43xx you can use, but some of these might be used for other functions (ie, board setup code normally uses divider E for SPIFI clocking setup). If setting up a divider causes the system to crash, try using another divider.

Option 1: Connect the 204MHz main PLL to a divider input, set the divider to 3, and use the divider for the HSADC base clock. Gives 204 / 3 = 68Mhz.
Just make sure you aren't using those dividers for anything else!

Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_MAINPLL, 3); /* Setup divider A for main PLL rate divided by 3 */
Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, CLKIN_IDIVA, true, false); /* HSADC base clock = divider A input */

[WARNING: DO NOT USE THE OPTION 2 SEE POSTS BELOW FOR MORE INFORMATION]
Option 2: Use the USB PLL rate (typically 480MHz) with a divide by 6 to get 80MHz. (Note different dividers have different maximum divider values)

Chip_USB0_Init(); /* Sets USB PLL to 480Mhz */
Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_USBPLL, 6); /* Setup divider D for USB PLL rate divided by 6 */
Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, CLKIN_IDIVD, true, false); /* HSADC base clock = divider D input */

You can use the Chip_Clock_GetRate(CLK_ADCHS) to get the clock rate the HSADC is currently running at regardless of clock tree configuration.

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:06 GMT

Content originally posted in LPCWare by dmorse on Mon Jan 27 14:03:07 MST 2014
Thanks

I tried option 2 and Chip_Clock_GetRate(CLK_ADCHS) shows as 20Mhz which is better.
I do some more debugging to see why..

If I won;t to use a external clock can that be done?

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:06 GMT

Content originally posted in LPCWare by dmorse on Wed Jan 29 18:42:24 MST 2014
Using option 2 got the USB0 clock to report 480 MHz but the ADCHS reports 60 MHz.
I not sure how to setup the PLL's. I ran the PLL_diaglog and got the values for the mdec,ndec,pdec seli and etc.
Now I just need to write them to the proper register.

With 60Mhz ADCHS clock I did get the HSADC to capture data, I was able to capture and verify a 500khz 75/25 duty cycle square wave.
Any faster shows missing samples which maybe because I am not using the DAM to transfer the FIFO to memory but a simple copy.
Where can I find the header file for setting up the DMA? I have the UM10503.pdf which show the registers.

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:07 GMT

Content originally posted in LPCWare by akmarov on Thu Jan 30 03:39:57 MST 2014

Quote: dmorse
.... I did get the HSADC to capture data, I was able to capture and verify a 500khz 75/25 duty cycle square wave.

How you did get HSADC to capture data? Can you provide a code to get data from HSADC?

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:08 GMT

Content originally posted in LPCWare by dmorse on Thu Jan 30 09:57:15 MST 2014
I have modified the hsadc.c file in the periph_hsadc folder.
Attached is my version of the file.

It uses the uart2 on J3 of the LPC4370 .target LPC=Link3 board.
Pin 14 on J3 the connector is user to test the timer.

In the 'hsadc.c line 57 and 58:

captureCount = 1000;// capture this many data points * 2
matchV = 0xa;//Descriptor match value; sampling rate divider

Simple commands
[list=1]
[*]'a' to capture data
[*]'b' to print data to uart2 at 115200 baud
[*]'C' to clear data array for new capture
[/list]

Using putty I capture the data and import it to excel then plot it to verify the results.

Now I just need to figure out how to us the DMA (right now I just copy from the FIFO's to a memory array) and set the clock for 80M samples.

Anyone have a something on the DMA?

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:08 GMT

Content originally posted in LPCWare by sundarapandian on Thu Jan 30 11:53:07 MST 2014

Quote:
I tried option 2 and Chip_Clock_GetRate(CLK_ADCHS) shows as 20Mhz which is better.
I do some more debugging to see why..

I think you might not be getting 20 MHz you will be getting 2MHz, as the only divider that can be sourced from USB0PLL is Divider A (Max divider value supported by DIV_A is 4), if you attempt to source others [DIV_B to DIV_D] from USB0PLL it will default to IRC (12MHz). Hence you will get "IRC CLK"/6 as the output. To get 80 MHz you can try the following

Chip_USB0_Init(); /* Initialize the USB0 PLL to 480 MHz */
Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 2); /* Source DIV_A from USB0PLL, and set divider to 2 (Max div value supported is 4)  [IN 480 MHz; OUT 240 MHz */
Chip_Clock_SetDivider(CLK_IDIV_B, CLKIN_IDIVA, 3); /* Source DIV_B from DIV_A, [IN 240 MHz; OUT 80 MHz */
Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, CLKIN_IDIVB, true, false); /* Source ADHCS base clock from DIV_B */
Chip_Clock_EnableOpts(CLK_ADCHS, true, true, 1); /* Enable the clock */

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:09 GMT

Content originally posted in LPCWare by dmorse on Thu Jan 30 12:59:37 MST 2014
Thanks you, That worked I now have ADCHS clock = 80MHz.

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:09 GMT

Content originally posted in LPCWare by nmz787 on Fri Jan 31 00:18:05 MST 2014
Glad to see you're making progress!

The LabTool code uses DMA, though they're using USB (the driver is provided by NXP, and the GUI source is provided too, with instructions for how to build on Windows. GUI readme:
https://github.com/embeddedartists/labtool/blob/master/app/COMPILE.md

Wow and there's even a lookup table for the PLL frequencies;
https://github.com/embeddedartists/labtool/blob/master/fw/program/source/capture.c#L115

Here's the DMA IRQ:
https://github.com/embeddedartists/labtool/blob/master/fw/program/source/capture_vadc.c#L198

Here's the DMA setup:
https://github.com/embeddedartists/labtool/blob/master/fw/program/source/capture_vadc.c#L468

Searching the labtool/fw/program directory with

grep -r DMA ./ |grep -v \.h |cut -d':' -f 1|uniq

outputs this list of files that refer to DMA (not including .h files, that's what the grep -v \.h gets rid of):

./sct/sct_fsm.c
./source/capture_sgpio.c
./source/capture_vadc.c
./source/generator_sgpio.c
./source/main.c
./source/startup_LPC43xx.s
./uVision/Internal_SRAM/firmware.map
./uVision/Internal_SRAM/startup_lpc43xx.lst

Best of luck, let us know when you get somewhere! I wish I had more time to program these days, but glad to help pull data together for others! When my class ends in a few months I'll be able to get to programming more!

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:10 GMT

Content originally posted in LPCWare by akmarov on Fri Jan 31 07:11:45 MST 2014
dmorse, I can't compile the project with your modified hsadc.c in Keil 4.73. I've got 14 errors, all looks like this:
#268: declaration may not appear after executable statement in block char countC[32] = "";///

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:11 GMT

Content originally posted in LPCWare by dmorse on Fri Jan 31 08:49:43 MST 2014
This was done in the LPCXpresso IDE.

char countC[32} = "";

This just creates a null string the size of 32 chars;
I did it this way because I could figure out how to declare a string in C.
The code is C not CPP..

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:11 GMT

Content originally posted in LPCWare by akmarov on Fri Jan 31 12:14:42 MST 2014
I've managed to compile your code and load it in microcontroller, but I don't understand what HSADC input do you use.

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:12 GMT

Content originally posted in LPCWare by dmorse on Fri Jan 31 14:19:16 MST 2014
I used ADC0 and ADC3 as differential.
J4 pin 4 as the Pos input and J4 pin 10 as Neg input.

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:13 GMT

Content originally posted in LPCWare by akmarov on Fri Jan 31 16:10:31 MST 2014
Really? I've viewed the code that you gave to me earlier (http://www.lpcware.com/system/files/hsadc_0.c) and found this:

/* Select both positive and negative DC biasing for input 3 */
Chip_HSADC_SetACDCBias(LPC_ADCHS, 1, HSADC_CHANNEL_NODCBIAS, HSADC_CHANNEL_NODCBIAS);

but this is not related to input 3, it is related to input 1.

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:13 GMT

Content originally posted in LPCWare by akmarov on Sat Feb 01 09:20:34 MST 2014
Finally I've got some adequate results. ADCHS clock is 80MHz, but sample rate is only 40Msps, not 80Msps as I expected. Every time I've tried to set SAMPLERATE to values more than 4000000 - UART stopped working. Is it real to get 80Msps?

I've added my version of hsadc.c . It is just a composition of what dmorse and sundarapandian have done, and it can be compiled in Keil 4.73 without errors.

Re: LPC4370 ACDHS speed

lpcware — Wed, 15 Jun 2016 19:08:14 GMT

Content originally posted in LPCWare by nmz787 on Sat Feb 01 21:18:36 MST 2014
well max CPU clock is 204 MHz, right? Can you try setting the ADC clock to 160MHz or something around there?