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    <title>LPC Microcontrollers中的主题 LPC4337 and SSD1963</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4337-and-SSD1963/m-p/582144#M20601</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by Bladerunner_Mike on Sun Jan 26 19:56:02 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;We've attached SSD1963 based tft dsyplay to EMC (signals: D15..D0 , RD#, WR#, CS#, A2). Dysplay require 8080-like bus for communication. In the 8080-mode interface consist of CS#, D/C#, RD#, WR#, D[16(8,9,24):0]&amp;nbsp; This interface use WR# to define a write cycle and RD# for read cycle. If the WR# goes low when the CS# signal is low, the data or command will be latched into the &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;system at the rising edge of WR#. Similarly, the read cycle will start when RD# goes low and end at the &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;rising edge of RD#. But interval between edges of WR# and CS# is too small, these signals are quite synchronous. &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;STRONG&gt;How to increase this interval? &lt;/STRONG&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The code of static init is following:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;DIV class="j-rte-table"&gt;&lt;TABLE border="1"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD bgcolor="#cacaca" style="border:1px solid black;background-color:#cacaca;border:1px solid black;background-color:#cacaca;border:1px solid black;background-color:#cacaca;background-color:#cacaca;border:1px solid black;background-color:#cacaca;border:1px solid black;background-color:#cacaca;border:1px solid black;"&gt; &lt;PRE&gt;void emcStaticInit ()
{
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICWAITWEN0_bit.WAITWEN&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0xF; //
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICWAITWR0_bit.WAITWR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x1F;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICWAITOEN0_bit.WAITOEN&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0xF;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICWAITPAGE0_bit.WAITPAGE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0xf;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICWAITTURN0_bit.WAITTURN&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x1f;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICWAITRD0_bit.WAITRD&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x1f;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICCONFIG0_bit.B&amp;nbsp; = 0x0;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICCONFIG0_bit.MW = 0x1;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICCONFIG0_bit.PM = 0x0;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICCONFIG0_bit.PB = 0x1;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 

}&lt;/PRE&gt; &lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In previous project we used GPIO for emulation 8080 bus interface, and initialization code of SSD1963 work well, and we could control diagrams of CS# WR# and D, A.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 19:07:53 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T19:07:53Z</dc:date>
    <item>
      <title>LPC4337 and SSD1963</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4337-and-SSD1963/m-p/582144#M20601</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by Bladerunner_Mike on Sun Jan 26 19:56:02 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;We've attached SSD1963 based tft dsyplay to EMC (signals: D15..D0 , RD#, WR#, CS#, A2). Dysplay require 8080-like bus for communication. In the 8080-mode interface consist of CS#, D/C#, RD#, WR#, D[16(8,9,24):0]&amp;nbsp; This interface use WR# to define a write cycle and RD# for read cycle. If the WR# goes low when the CS# signal is low, the data or command will be latched into the &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;system at the rising edge of WR#. Similarly, the read cycle will start when RD# goes low and end at the &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;rising edge of RD#. But interval between edges of WR# and CS# is too small, these signals are quite synchronous. &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;STRONG&gt;How to increase this interval? &lt;/STRONG&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The code of static init is following:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;DIV class="j-rte-table"&gt;&lt;TABLE border="1"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD bgcolor="#cacaca" style="border:1px solid black;background-color:#cacaca;border:1px solid black;background-color:#cacaca;border:1px solid black;background-color:#cacaca;background-color:#cacaca;border:1px solid black;background-color:#cacaca;border:1px solid black;background-color:#cacaca;border:1px solid black;"&gt; &lt;PRE&gt;void emcStaticInit ()
{
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICWAITWEN0_bit.WAITWEN&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0xF; //
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICWAITWR0_bit.WAITWR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x1F;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICWAITOEN0_bit.WAITOEN&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0xF;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICWAITPAGE0_bit.WAITPAGE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0xf;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICWAITTURN0_bit.WAITTURN&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x1f;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICWAITRD0_bit.WAITRD&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x1f;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICCONFIG0_bit.B&amp;nbsp; = 0x0;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICCONFIG0_bit.MW = 0x1;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICCONFIG0_bit.PM = 0x0;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; EMC_STATICCONFIG0_bit.PB = 0x1;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 

}&lt;/PRE&gt; &lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In previous project we used GPIO for emulation 8080 bus interface, and initialization code of SSD1963 work well, and we could control diagrams of CS# WR# and D, A.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:07:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4337-and-SSD1963/m-p/582144#M20601</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:07:53Z</dc:date>
    </item>
    <item>
      <title>Re: LPC4337 and SSD1963</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4337-and-SSD1963/m-p/582145#M20602</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by rocketdawg on Mon Jan 27 10:28:01 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;you need to insert NOPs in between the lines of code.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;depending upon compiler, some thing like&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;asm volatile ("mov r0,r0");&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;will add one clock&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;EMC_STATICWAITWEN0_bit.WAITWEN&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0xF; //&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;asm volatile ("mov r0,r0");&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;asm volatile ("mov r0,r0");&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;asm volatile ("mov r0,r0");&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;asm volatile ("mov r0,r0");&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;EMC_STATICWAITWR0_bit.WAITWR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x1F;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;will add 4 clocks&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:07:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4337-and-SSD1963/m-p/582145#M20602</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:07:54Z</dc:date>
    </item>
    <item>
      <title>Re: LPC4337 and SSD1963</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4337-and-SSD1963/m-p/582146#M20603</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by Bladerunner_Mike on Mon Jan 27 19:22:25 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Everything is OK! Very &lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:07:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC4337-and-SSD1963/m-p/582146#M20603</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:07:55Z</dc:date>
    </item>
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