topic SCB (System control block) missing in User manual (UM10503) in LPC Microcontrollers

SCB (System control block) missing in User manual (UM10503)

lpcware — Wed, 15 Jun 2016 19:07:29 GMT

Content originally posted in LPCWare by metraTec on Tue Feb 16 07:27:20 MST 2016
Hello everybody,
started working with the LPC4370 and just found this problem:

SCB is nowhere to be found. But it is required and named in some context like Sleep, CPUID, Reset.
It is also in the CMSIS / library header files. But I really like a definition. Don't like to guess the exact positions and meaning of functions.

Both in revision 2.0 from november and 2.1 from december 2015.

To find positions it is mentioned search for "SLEEPDEEP" in in UM.

Have a nice day anyways

Re: SCB (System control block) missing in User manual (UM10503)

lpcware — Wed, 15 Jun 2016 19:07:31 GMT

Content originally posted in LPCWare by vtw.433e on Tue Feb 16 09:10:06 MST 2016
Do you mean the system control unti (SCU) - Chapter 17?

If not, what are you missing?

Re: SCB (System control block) missing in User manual (UM10503)

lpcware — Wed, 15 Jun 2016 19:07:31 GMT

Content originally posted in LPCWare by metraTec on Tue Feb 16 09:36:51 MST 2016
No, I'm not meaning that unit. I have seen the naming though.

I miss the SCB (known to me from LPC122x I worked with before) which I also found in the "core_cm0.h" and "core_cm4.h". Both entries differ a bit. I just copy the important things:

From "core_cm4.h":

/** \ingroup CMSIS_core_register
    \defgroup CMSIS_SCB CMSIS SCB
Type definitions for the Cortex-M System Control Block Registers
@{
*/

/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID;                   /*!< Offset: 0x000 (R/ ) CPUID Base Register                                   */
__IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W) Interrupt Control and State Register                  */
__IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W) Vector Table Offset Register                          */
__IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register      */
__IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W) System Control Register                               */
__IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W) Configuration Control Register                        */
__IO uint8_t SHP[12];                 /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W) System Handler Control and State Register             */
__IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W) Configurable Fault Status Register                    */
__IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W) HardFault Status Register                             */
__IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W) Debug Fault Status Register                           */
__IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W) MemManage Fault Address Register                      */
__IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W) BusFault Address Register                             */
__IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register                       */
__I uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ ) Processor Feature Register                            */
__I uint32_t DFR;                     /*!< Offset: 0x048 (R/ ) Debug Feature Register                                */
__I uint32_t ADR;                     /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register                            */
__I uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ ) Memory Model Feature Register                         */
__I uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register                   */
       uint32_t RESERVED0[5];
__IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register                   */
} SCB_Type;

/***********END******************/

From "core_cm0.h":

/** \ingroup CMSIS_core_register
    \defgroup CMSIS_SCB CMSIS SCB
Type definitions for the Cortex-M System Control Block Registers
@{
*/

/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID;                   /*!< Offset: 0x000 (R/ ) CPUID Base Register                                   */
__IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W) Interrupt Control and State Register                  */
       uint32_t RESERVED0;
__IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register      */
__IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W) System Control Register                               */
__IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W) Configuration Control Register                        */
       uint32_t RESERVED1;
__IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED   */
__IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W) System Handler Control and State Register             */
} SCB_Type;

/***********END******************/

Also: in both:
#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
#define SCB_BASE            (SCS_BASE + 0x0D00UL)                    /*!< System Control Block Base Address */

Important things I miss:
CPUID, SLEEPDEEP bit (in SCR), AIRCR (for resetting)

Re: SCB (System control block) missing in User manual (UM10503)

lpcware — Wed, 15 Jun 2016 19:07:32 GMT

Content originally posted in LPCWare by vtw.433e on Tue Feb 16 10:16:59 MST 2016
The LPC43xx does not have an SCB - that is why it is not documented!

It is a different chip - you are going to have to re-write your code.

Re: SCB (System control block) missing in User manual (UM10503)

lpcware — Wed, 15 Jun 2016 19:07:33 GMT

Content originally posted in LPCWare by mysepp on Tue Feb 16 10:35:15 MST 2016
Are you sure?

This page is for Cortex-M4 in general:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/CIHFDJCA.html

When I look into some of my old sources, I see I used e.g. MMFAR. But sorry, can't remember if it worked.
But it was with a old lpc43xx.h, which used something like

#define MMFAR                (*(volatile unsigned long *)(0xE000ED34))

instead of CMSIS way

SCB->MMFAR

Perhaps you can try

#define CPUID                (*(volatile unsigned long *)(0xE000ED00))
#define AIRCR                (*(volatile unsigned long *)(0xE000ED0C))

and see if it is working or not...good luck!

Would be nice if you can give some feedback on this topic.

Just a note due to AIRCR: Have a look at the errata of LPC4357 for RESET.x,
but it does not seem to affect AIRCR, but NVIC_SystemReset() using PERIPH_RST.

Re: SCB (System control block) missing in User manual (UM10503)

lpcware — Wed, 15 Jun 2016 19:07:33 GMT

Content originally posted in LPCWare by vtw.433e on Tue Feb 16 10:51:40 MST 2016
Your're right - I was confusing with something else. Ignore my previous post.

Re: SCB (System control block) missing in User manual (UM10503)

lpcware — Wed, 15 Jun 2016 19:07:34 GMT

Content originally posted in LPCWare by metraTec on Wed Feb 17 01:42:49 MST 2016
The debugger also knows about this registers (Peripherals, area NVIC).
I dont have to do the define, I have them in the lib /CMSIS anyways. But its a documentation feedback. Its annoying to not find the needed registers in the UM.

Re: SCB (System control block) missing in User manual (UM10503)

lpcware — Wed, 15 Jun 2016 19:07:35 GMT

Content originally posted in LPCWare by metraTec on Wed Feb 17 01:46:07 MST 2016
Looks like the CPUID is core dependent. Have just looked at M4 and M0Sub with the debugger. They differ.

Can I use this for library (checking the CPUID to get for example the correct core clock?)

Re: SCB (System control block) missing in User manual (UM10503)

lpcware — Wed, 15 Jun 2016 19:07:35 GMT

Content originally posted in LPCWare by TheFallGuy on Wed Feb 17 02:39:59 MST 2016
SCB is part of the core (Cortex-M4/Cortex-M3/Cortex-M0/etc) from ARM. This is documented in ARM documentation. NXP (inconsistently, but as a general principle) do not document ARM core functions in their documentation.

As CPUID is related to the core then it will tell you whether you are running on the M4 or the M0. However, beware that some LPC43xx parts have 3 cores - 1xM4 and 2xM0's, so be careful as both M0's will return the same CPUID!