topic Re: Wrong LPC11xx Chip_TIMER_ClearCapture function in LPC Microcontrollers

Wrong LPC11xx Chip_TIMER_ClearCapture function

lpcware — Wed, 15 Jun 2016 20:18:39 GMT

Content originally posted in LPCWare by R2D2 on Tue Jul 14 03:25:34 MST 2015
timer_11xx.h of lpcopen_v2_00a_lpcxpresso_nxp_lpcxpresso_11c24.zip
is including a wrong clear capture interrupt function:

STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->IR = [color=#f00](0x10 << capnum);[/color]
}

Corrected:

STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->IR =[color=#090] TIMER_CAP_INT(capnum);[/color]
}

BTW: the new 2015 version lpcopen_2_17_lpcxpresso_nxp_lpcxpresso_1125.zip is including the same error :~ :(( :quest:

So probably all LPC11 versions are including this surprise...

Re: Wrong LPC11xx Chip_TIMER_ClearCapture function

lpcware — Wed, 15 Jun 2016 20:18:40 GMT

Content originally posted in LPCWare by cappo85 on Tue Jul 14 07:16:49 MST 2015
Hi,

why it does not works?

when capnum is:
0 -> 0x10<<0 = 0x10, so you clear bit 4
1 -> 0x10<<1 = 0x20, so you clear bit 5
2 -> 0x10<<1 = 0x40, so you clear bit 6

is not correct?

Best Regards
Riccardo Capponi

Re: Wrong LPC11xx Chip_TIMER_ClearCapture function

lpcware — Wed, 15 Jun 2016 20:18:40 GMT

Content originally posted in LPCWare by NXP_Support on Tue Jul 14 13:01:00 MST 2015
Hi R2D2,

I assume you ran into a problem somewhere, but I have to agree with Riccardo on this one. The Interrupt flag for clearing a capture channel event starts at bit position 4 (0x10). The code works as is (and is highly efficient ;-) ). From the LPC11Cxx UM:

Table 314: Interrupt Register (TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000) bit
description
Bit   Symbol Description                                                            Reset value
0      MR0 Interrupt Interrupt flag for match channel 0.              0
1      MR1 Interrupt Interrupt flag for match channel 1.              0
2      MR2 Interrupt Interrupt flag for match channel 2.              0
3      MR3 Interrupt Interrupt flag for match channel 3.              0
4      CR0 Interrupt Interrupt flag for capture channel 0 event.   0
31:5 - Reserved

Please let us know if we have misunderstood the problem.
Best regards,
-NXP Support