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    <title>topic Timer/RIT: write clear interrupt flag to 1, read as 0, when? in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Timer-RIT-write-clear-interrupt-flag-to-1-read-as-0-when/m-p/576569#M19465</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by petekol on Sun Nov 01 07:04:59 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;i have some understanding problem of clearing an interrupt flag of RIT:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;i expect that harware clears the flag to 0 and a can read it as 0 after i write 1 to it. In practice i do not read 0 event if doing it in a loop for ever (in ISR).&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Does it means that it is acctually cleared internally by writing 1 an i can't read it as 0 (only after exit from ISR?) but if i move compare value then it fire interrupt next time.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;So tha question is when i should expect to read the flag as 0? Before this time and after i write 1 to it can i trigger one more compare fire (flag goes to 1)?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thnx&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Lok&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 19:01:59 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T19:01:59Z</dc:date>
    <item>
      <title>Timer/RIT: write clear interrupt flag to 1, read as 0, when?</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Timer-RIT-write-clear-interrupt-flag-to-1-read-as-0-when/m-p/576569#M19465</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by petekol on Sun Nov 01 07:04:59 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;i have some understanding problem of clearing an interrupt flag of RIT:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;i expect that harware clears the flag to 0 and a can read it as 0 after i write 1 to it. In practice i do not read 0 event if doing it in a loop for ever (in ISR).&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Does it means that it is acctually cleared internally by writing 1 an i can't read it as 0 (only after exit from ISR?) but if i move compare value then it fire interrupt next time.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;So tha question is when i should expect to read the flag as 0? Before this time and after i write 1 to it can i trigger one more compare fire (flag goes to 1)?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thnx&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Lok&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:01:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Timer-RIT-write-clear-interrupt-flag-to-1-read-as-0-when/m-p/576569#M19465</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:01:59Z</dc:date>
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