LPC MicrocontrollersのトピックSCT on LPC824

SCT on LPC824

lpcware — Wed, 15 Jun 2016 20:14:47 GMT

Content originally posted in LPCWare by sanders7284 on Tue Oct 13 07:41:42 MST 2015
Hello, I am having some trouble geting a capture compare to run using the SCT,

I think the problem my be linked to the pin assignment but have included the full init of the SCT below,

Event 0 the 400uS match and reload aspect is working perfectly it is event 1 and the capture funtion that are not, no IRQ is generated.

//TIMER_INIT -------------------------------------------------------------------
void TIMER_INIT()
{
//setup ----------------------------------------------------------------------
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SCT);
Chip_SYSCTL_PeriphReset(RESET_SCT); // Initialize the SCT clock and reset the SCT
Chip_SCT_Config(SCT_CONFIG_32BIT_COUNTER | SCT_CONFIG_CLKMODE_BUSCLK); // Configure the SCT counter as a unified (32 bit) counter using the bus clock
LPC_SCT->REGMODE_L = 0x0002; //0 is match, 1 is capcom

//set 0 to be 400uS sample timer for bit measuring ---------------------------
Chip_SCT_SetMatchCount(SCT_MATCH_0, SystemCoreClock / TICKRATE_HZ); // Set the match count for match register 0
Chip_SCT_SetMatchReload(SCT_MATCH_0, SystemCoreClock / TICKRATE_HZ); // Set the match reload value for match reload register 0
LPC_SCT->EVENT[0].CTRL = (1 << 12); // Event 0 only happens on a match condition
LPC_SCT->EVENT[0].STATE = 0xFFFFFFFF; // Event 0 happens in all states
LPC_SCT->LIMIT_L = 0x0001; /// Event 0 is used as the counter limit (each bit relates to an event bit 0 for event 0)

//set 1 to be capture compare for falling edge -------------------------------
LPC_SCT->EVENT[1].STATE = 0xFFFFFFFF; // Event 1 only happens in state 0
LPC_SCT->CAPCTRL[1].U = 0x00000001; //Event 1
LPC_SCT->EVENT[1].CTRL = (2 << 10) | (2 << 12); //set IOCOND to falling edge capture & set COMBMODE to IO condition only

Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM); // Enable SWM clock before altering SWM
Chip_SWM_MovablePinAssign(SWM_SCT_IN0_I, 23); //assigne p0.23 to link to IN0 for capcom.
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM); // Disable SWM clock after altering SWM

//go timer -------------------------------------------------------------------
Chip_SCT_EnableEventInt(SCT_EVT_0); // Enable flag to request an interrupt for Event 0
Chip_SCT_EnableEventInt(SCT_EVT_1); // Enable flag to request an interrupt for Event 1
NVIC_EnableIRQ(SCT_IRQn); // Enable the interrupt for the SCT
NVIC_SetPriority(SCT_IRQn, 3);
Chip_SCT_ClearControl(SCT_CTRL_HALT_L); // Start the SCT counter by clearing Halt_L in the SCT control register
}
//------------------------------------------------------------------------------

Cheers Sanders

Re: SCT on LPC824

lpcware — Wed, 15 Jun 2016 20:14:48 GMT

Content originally posted in LPCWare by sanders7284 on Fri Oct 16 02:56:01 MST 2015
I have figured out that the INMUX also needs setting up on the LPC824 so the capture compare is now running but it seems to be missing some edges.

I have included the code as it stands and some scope shots of the problem, it is not periodic so I don't think it is a timer overflow type error but am stuggling to put my finger on what it could be.

//TIMER_INIT -------------------------------------------------------------------
void TIMER_INIT()
{
//setup ----------------------------------------------------------------------
Chip_SCT_Init(LPC_SCT);
Chip_SYSCTL_PeriphReset(RESET_SCT); // Initialize the SCT clock and reset the SCT
Chip_SCT_Config(LPC_SCT, (SCT_CONFIG_32BIT_COUNTER | SCT_CONFIG_CLKMODE_BUSCLK)); // Configure the SCT counter as a unified (32 bit) counter using the bus clock
LPC_SCT->REGMODE_L = 0x0002; //0 is match, 1 is capcom
LPC_SCT->STATE_U = 0;

//set 0 to be 400uS sample timer for bit measuring ---------------------------
//Chip_SCT_SetMatchCount(LPC_SCT, SCT_MATCH_0, (SystemCoreClock / Limit_1S)); // Set the match count for match register 0
//Chip_SCT_SetMatchReload(LPC_SCT, SCT_MATCH_0, SystemCoreClock / Limit_1S); // Set the match reload value for match reload register 0
//LPC_SCT->EV[0].CTRL = (1 << 12); // Event 0 only happens on a match condition
//LPC_SCT->EV[0].STATE = 0x02; // Event 0 happens in state 1
//LPC_SCT->LIMIT_L = 0x0001; /// Event 0 used as the counter limit (each bit relates to an event bit 0 for event 0)

//set 1 to be capture compare for falling edge -------------------------------
LPC_SCT->EV[1].STATE = 0x01; // Event 1 only happens in state 0
LPC_SCT->CAPCTRL[1].U = 0x00000001; //Event 1
LPC_SCT->EV[1].CTRL = (2 << 10) | (2 << 12); //set IOCOND to falling edge capture & set COMBMODE to IO condition only

Chip_SWM_Init(); // Enable SWM clock before altering SWM
Chip_SWM_MovablePinAssign(SWM_SCT_IN0_I, 23); //assigne p0.23 to link to IN0 for capcom.
LPC_INMUX->SCT0_INMUX[0] = 0;
Chip_SWM_Deinit(); // Disable SWM clock after altering SWM

//go timer -------------------------------------------------------------------
//Chip_SCT_EnableEventInt(LPC_SCT, SCT_EVT_0); // Enable flag to request an interrupt for Event 0
Chip_SCT_EnableEventInt(LPC_SCT, SCT_EVT_1); // Enable flag to request an interrupt for Event 1
NVIC_EnableIRQ(SCT_IRQn); // Enable the interrupt for the SCT
NVIC_SetPriority(SCT_IRQn, 3);
Chip_SCT_ClearControl(LPC_SCT, SCT_CTRL_HALT_L); // Start the SCT counter by clearing Halt_L in the SCT control register
}
//------------------------------------------------------------------------------