LPC MicrocontrollersのトピックLPC7399

LPC7399

lpcware — Wed, 15 Jun 2016 18:56:56 GMT

Content originally posted in LPCWare by hlsa on Wed Sep 24 05:48:19 MST 2014
After reading abou the new ARM Cortex M7 yesterday, I am looking forward to get the LPC7399. Here some technical details:

[list]
[*]Quad core MCU with one M7 core and three M0 cores running at 300 MHz.
[*]3 MB integrated Flash Memory
[*]Dedicated Crc unit for Hardware based CRC16 / CRC32 calculations.
[*]32 channel DMA Controller
[*]4 U(S)ART Interfaces @ 20 MBit/s
[*]Other peripherals similar to LPC4357
[/list]

Oops. Just a dream. ;-) ... But maybe it is good to give NXP some time to develop it properly (nothing worse than a lot of errata).

Re: LPC7399

lpcware — Wed, 15 Jun 2016 18:56:57 GMT

Content originally posted in LPCWare by Benjamin Vernoux on Wed Sep 24 15:10:11 MST 2014
LPC7xxx DualCore Cortex M7 min @400MHz (and up to 800MHz) + 1 M0+ for peripherals with following features:
- An updated dual SGPIO (up to Dual 16bits + Clocks) to offer 12 an 16bits !! instead of a limitation to 8bits mode in order to interface with a modern 16bits DAC + 16bits ADC > 20MSPS
- ADC HS 20MSPS 16bits (or 40MSPS 12bits) including configurable hardware decimation and filter.
- DAC HS 80MSPS 16bits.
- Dual Hardware FIFO peripheral with configurable addr+size in SRAM/SDRAM area + DMA.
- Ethernet Gigabit with HW ip/udp packet+crc (will be a must for realtime data).
- Dual integrated USB 2.0 HS PHY (instead of having only 1 integrated HS PHY).
- USB3.1 Device, even if it is limited by the bus/mcu to something like 200Mbytes/s will be a must for realtime data.
- More SRAM (512KB total will be a must) + more banks on different dedicated bus.

Re: LPC7399

lpcware — Wed, 15 Jun 2016 18:56:57 GMT

Content originally posted in LPCWare by JohnR on Thu Sep 25 05:50:35 MST 2014
Hi,

Quote:
An updated dual SGPIO (up to Dual 16bits + Clocks) to offer 12 an 16bits !! instead of a limitation to 8bits mode in order to interface with a modern 16bits DAC + 16bits ADC > 20MSPS

Add the ability tor reverse the direction of the shift registers to accommodate both MSB and LSB serial data.

John.

Re: LPC7399

lpcware — Wed, 15 Jun 2016 18:56:58 GMT

Content originally posted in LPCWare by rocketdawg on Sun Oct 05 12:58:07 MST 2014

Quote: Benjamin Vernoux

LPC7xxx DualCore Cortex M7 min @400MHz (and up to 800MHz) + 1 M0+ for peripherals with following features:
- ADC HS 20MSPS 16bits (or 40MSPS 12bits) including configurable hardware decimation and filter.
- DAC HS 80MSPS 16bits.
- More SRAM (512KB total will be a must) + more banks on different dedicated bus.

drop the M0+. Have parts that add a optional M3, or M4. Vybrid does an A5/M4.
Since the LPC4370 already does 80 MSPS ADC, I would say that is a minimum.
PIC32MZ has 512K RAM, but it is so damaged by errata.
and make some of the RAM more contiguous. The LPC43xx memory map is a bit disjointed.

Re: LPC7399

lpcware — Wed, 15 Jun 2016 18:56:59 GMT

Content originally posted in LPCWare by Pacman on Mon Oct 06 21:45:55 MST 2014
If you want to go beyond 400MHz, the microcontroller will cost a lot more.
This is because the 28nm will go up to 400MHz, but of course if you're speaking about 10nm technology, you'll be able to get past the 400MHz limit. ;)
-We'll need to keep the price of the M7 below the A5 too. :)

I'm pretty confident that you would be able to do 400M memory operations per second with the 400MHz Cortex-M7, because it has a dual ALU.

SRAM: Agree: More SRAM. 512kB if possible - and contigous. I don't care about Flash memory, as long as there's more than 8kB.
Flash memory isn't really important for me.
It's possible to run high-speed subroutines from SRAM; which is impossible to do in Flash, due to the delay.
So 3MB Flash memory is way over my needs (I don't need to install Windows or put uncompressed pictures in there).
I'd prefer having 8kB Flash and then 256kB or 512kB SRAM compared to 4MB Flash and 240kB SRAM.
-Because I can always interface external memory (such as SPI, SPIFI, SD/MMC, NAND or NOR) without losing much speed.
The speed will be gained back when copying a routine to SRAM temporarily and throwing it away after use.

Note: I'm not saying that there should be no Flash memory at all. I'm just emphasizing how important SRAM is to me.
I would not mind having 128kB Flash memory or more.

DACS: Agree, but I'd prefer 6 of them.

And as JohnR says ... SGPIO should have an option for lsb/msb first, plus an extra option for byte-reversing (4 combinations)
(perhaps being able to control each SGPIO line's bit stream individually, in order to allow multiple interface types at the same time)

Enhanced DMA would be real cool [eg. repeat-count with interleave-increment for each transfer on both source and destination, so you wouldn't have to have 500+ LLIs], but as this is ARM's technology, it's ARM that needs to enhance it.
Yes, and dual logical (AND/OR/XOR) operations on each DMA transfer too one for first transfer, one for next N transfers and one for the last transfer - on both source and destination - I know, I know, I'm asking for too much here.