LPC Microcontrollers中的主题 mixing up data lines at SDRAM https://community.nxp.com/t5/LPC-Microcontrollers/mixing-up-data-lines-at-SDRAM/m-p/571521#M18403 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by khfreiberg on Wed Mar 19 15:17:25 MST 2014</STRONG><BR /><SPAN>Hi,</SPAN><BR /><SPAN>I have a question to layout optimization.</SPAN><BR /><SPAN>At normal SRAM it is no problem to mixup the data lines, since it comes out as it got in.</SPAN><BR /><SPAN>I have two 16bit SDRAMS to form a 32bit bus (using CLK1/CLK3). I have seen AN10935, AN10778 and AN11508.</SPAN><BR /><SPAN>The SDRAM layout is quite critical concerning length matching so I would like to optimize by swapping data lines. I did not found an exact description how the EMC deals with DMQOUT lines. I assume in 32bit configuration DMQOUT0...3 are driven in parallel. Looks like there is nothing that prevent me from doing this. Do I miss something ?&nbsp; </SPAN></BODY></HTML> Wed, 15 Jun 2016 18:55:58 GMT lpcware 2016-06-15T18:55:58Z mixing up data lines at SDRAM https://community.nxp.com/t5/LPC-Microcontrollers/mixing-up-data-lines-at-SDRAM/m-p/571521#M18403 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by khfreiberg on Wed Mar 19 15:17:25 MST 2014</STRONG><BR /><SPAN>Hi,</SPAN><BR /><SPAN>I have a question to layout optimization.</SPAN><BR /><SPAN>At normal SRAM it is no problem to mixup the data lines, since it comes out as it got in.</SPAN><BR /><SPAN>I have two 16bit SDRAMS to form a 32bit bus (using CLK1/CLK3). I have seen AN10935, AN10778 and AN11508.</SPAN><BR /><SPAN>The SDRAM layout is quite critical concerning length matching so I would like to optimize by swapping data lines. I did not found an exact description how the EMC deals with DMQOUT lines. I assume in 32bit configuration DMQOUT0...3 are driven in parallel. Looks like there is nothing that prevent me from doing this. Do I miss something ?&nbsp; </SPAN></BODY></HTML> Wed, 15 Jun 2016 18:55:58 GMT https://community.nxp.com/t5/LPC-Microcontrollers/mixing-up-data-lines-at-SDRAM/m-p/571521#M18403 lpcware 2016-06-15T18:55:58Z