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    <title>LPC MicrocontrollersのトピックDo all the Freescale/NXP ARM Cores permit write-thru cache policy? From ARM documents A-7 seems to.</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Do-all-the-Freescale-NXP-ARM-Cores-permit-write-thru-cache/m-p/571495#M18394</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;According to ARM, A-7 permits write-thru cache policy. Does LS1022A implement this? What about other Freescale/NXP ARM cores?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 04 Aug 2016 16:32:00 GMT</pubDate>
    <dc:creator>Rusty</dc:creator>
    <dc:date>2016-08-04T16:32:00Z</dc:date>
    <item>
      <title>Do all the Freescale/NXP ARM Cores permit write-thru cache policy? From ARM documents A-7 seems to.</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Do-all-the-Freescale-NXP-ARM-Cores-permit-write-thru-cache/m-p/571495#M18394</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;According to ARM, A-7 permits write-thru cache policy. Does LS1022A implement this? What about other Freescale/NXP ARM cores?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 04 Aug 2016 16:32:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Do-all-the-Freescale-NXP-ARM-Cores-permit-write-thru-cache/m-p/571495#M18394</guid>
      <dc:creator>Rusty</dc:creator>
      <dc:date>2016-08-04T16:32:00Z</dc:date>
    </item>
    <item>
      <title>Re: Do all the Freescale/NXP ARM Cores permit write-thru cache policy? From ARM documents A-7 seems to.</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Do-all-the-Freescale-NXP-ARM-Cores-permit-write-thru-cache/m-p/571496#M18395</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt; background: white;"&gt;Look at the following page from ARM Community:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt; background: white;"&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fcommunity.arm.com%2Fthread%2F5003" rel="nofollow" target="_blank"&gt;https://community.arm.com/thread/5003&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Pavel Chubakov&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 11 Aug 2016 05:54:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Do-all-the-Freescale-NXP-ARM-Cores-permit-write-thru-cache/m-p/571496#M18395</guid>
      <dc:creator>Pavel</dc:creator>
      <dc:date>2016-08-11T05:54:09Z</dc:date>
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