LPC MicrocontrollersのトピックRe: Inverted SD_CLK on LPC4337

Inverted SD_CLK on LPC4337

lpcware — Wed, 15 Jun 2016 18:57:07 GMT

Content originally posted in LPCWare by jgorsk on Fri Oct 03 00:32:12 MST 2014
Is there any reason why SD_CLK line on the LPC4337 in LQFP144 would be inverted? When a command is sent to SD card,
active edge of SD_CLK is the falling edge. Therefore the card is not replying. When I delay SD_CMD slightly with a simple RC
circuit, the card actually starts replying.

This happens during the initialization of the card when the clock frequency is 400kHz. I'm using CLK0 pin for SD_CLK.

I'm running this on my own board with no SDRAM.

Re: Inverted SD_CLK on LPC4337

lpcware — Wed, 15 Jun 2016 18:57:08 GMT

Content originally posted in LPCWare by bavarian on Fri Oct 17 03:37:35 MST 2014
In order not to keep others in the dark on this issue 8-)

Using the negative edge of the clock is a way to arrange simple compliance to the 5ns hold requirement of the SD cards.
The IP block NXP used suggests a different solution. The IP block has internally 2 extra clocks. One is used for driving data to the outside and the other one for capturing data.
By delaying the driving clock you can generate the hold time. And by delaying the sample clock you can compensate for internal & external delays.
The control settings for these delays are not yet described in the UM :-(

Register address 0x4008 6D80 (default = 0x0)

bits 3..0 sdio_sample_delay
bits 11..8 sdio_drv_delay

The delay is about 0.5ns per step; the range is 0..15 x 0.5ns
Suggested settings are:
- sdio_sample_delay = 8
- sdio_drv_delay = 15

So write value 0x0F08 to address 0x4008 6D80.

Regards,
NXP Support Team.

Re: Inverted SD_CLK on LPC4337

lpcware — Wed, 15 Jun 2016 18:57:08 GMT

Content originally posted in LPCWare by jgorsk on Thu Oct 23 05:44:18 MST 2014
Thanks for your reply.

Let me say it again. I see the incorrect clock phase (falling edge) only during the SD card initialization phase when the clock
frequency is 400kHz. When that passes, the high speed communication has the correct clock phase (rising).

I actually have 0x0F08 in the register at address 0x4008 6D80 (register SDDELAY). That register is described
in the used manual. SDDELAY register has negligible effect on the clock phase at 400kHz.

So, is it correct that the the negative clock edge is the active edge during the initialization?

Is there any other register that's not described in the user manual yet that can influence the SD clock phase?