topic Re: address shift mode for different bus width in LPC Microcontrollers

address shift mode for different bus width

lpcware — Wed, 15 Jun 2016 17:22:48 GMT

Content originally posted in LPCWare by medicaltech_rovereto on Mon Jul 20 01:45:18 MST 2015
I am using a LPC1788 MCU.

I would like to interface it to:
[list]
a [u]32[/u] bit wide memory bank using two 16 bit SRAM memory chips and

to a [u]16[/u] bit wide memory bank using one 16 bit FLASH NOR memory chip
[/list]

Is it possible to use address lines [A0:A19] on the MCU side for both memory banks (one has a 32bit bus the other a 16bit bus ) and then enable "address shift mode" obtaining that for one bank the address are output shifted by 1 and for the other bank the addresses are output shifted by 2 ??

Is this possible or I have to do it Hardware?

Best regards

Re: address shift mode for different bus width

lpcware — Wed, 15 Jun 2016 17:22:49 GMT

Content originally posted in LPCWare by wmues on Mon Jul 20 05:19:46 MST 2015
There is no need to use "address shift mode".

Connect A2:A19 to the 2x16bit SRAM
and
Connext A1:A19 to the 16bit NOR Flash.

Address shift mode is only useful if you need the full amount of address lines to address your memory.

Re: address shift mode for different bus width

lpcware — Wed, 15 Jun 2016 17:22:50 GMT

Content originally posted in LPCWare by medicaltech_rovereto on Mon Jul 20 07:26:08 MST 2015
I know that it can be done hardware but in my case it is useful if it can be done SW.

Re: address shift mode for different bus width

lpcware — Wed, 15 Jun 2016 17:22:50 GMT

Content originally posted in LPCWare by MikeSimmonds on Mon Jul 20 08:51:06 MST 2015
I have exactly that configuration (two x 16 SDRAM = 32 bit bus; one of 16 static ram = 16 bit bus) but probably different devices and memory sizes.
I am using the address shift feature also. But not that the address shift only applies to the static ram, not the SDRAM!

I have A0-A18 for the static ram, and A0 to A12 for the SDRAM and you must have A13 to A14 for the Bank select bits BA0/1.
Line A12 is a no-connect (on the SDRAM), but allows for larger SDRAMs to be fitted without PCB revision.

SDRAM = 2 x MT48LC16M16 [256 Mbits each = 32 MB], SRAM = BS616LV4017EI [512K; 256Kx16].

Hope that helps.

EDIT: the address shift applies (or not) to all four Static Ram Chip selects -- cannot mix and match!

Mike.