<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>LPC MicrocontrollersのトピックIs that possible to build a SPI master/slave bus using SSP0/SSP1 on one board?</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Is-that-possible-to-build-a-SPI-master-slave-bus-using-SSP0-SSP1/m-p/568653#M17765</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by stanley76726 on Fri Oct 19 20:59:49 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hello!&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;For checking whether the SPI bus on LPC4357 is available, I am trying to use SSP0 as a master and SSP1 as a slave on the same board (MCB4300). &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;At first, I ran the Ssp_Master sample and check the waveforms (SCK, SSEL, and MOSI) from a oscilloscope, it seemed to work as expected.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;But since I am unsure whether the MISO/MOSI can receive data correctly and have only one board, I want to built a SPI master/slave bus on one board, as titled.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Therefore, I combined both Ssp_Master and Ssp_Slave samples into a progrom.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;My problem is that:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;When I was debugging using Keil uVision4, the SSP Data Register (SSPx-&amp;gt;DR) was wrote to some wrong values. Take Ssp_Master as an example, when it went in SSP_ReadWrite() -&amp;gt; SSP_SendData(), the value of SSPx-&amp;gt;DR was set to 0x80 or 0xFF, not 0x01~0x3F as I expected. On the other hand, the SSP Status Register SSPx-&amp;gt;SR was always 0x00000003 (meant to Transmit FIFO Empty(TFE) and Transmit FIFO Not Full(TNF)), SSPx-&amp;gt;SR should be written to 0x00000000 or 0x00000002 when the FIFO is full or is sent 1-7 data frame(s), isn't it?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Anyone have already run Ssp_Master/Ssp_Slave sampels on LPC43xx boards, or had similar experience? Share with me please!&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:52:10 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:52:10Z</dc:date>
    <item>
      <title>Is that possible to build a SPI master/slave bus using SSP0/SSP1 on one board?</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Is-that-possible-to-build-a-SPI-master-slave-bus-using-SSP0-SSP1/m-p/568653#M17765</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by stanley76726 on Fri Oct 19 20:59:49 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hello!&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;For checking whether the SPI bus on LPC4357 is available, I am trying to use SSP0 as a master and SSP1 as a slave on the same board (MCB4300). &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;At first, I ran the Ssp_Master sample and check the waveforms (SCK, SSEL, and MOSI) from a oscilloscope, it seemed to work as expected.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;But since I am unsure whether the MISO/MOSI can receive data correctly and have only one board, I want to built a SPI master/slave bus on one board, as titled.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Therefore, I combined both Ssp_Master and Ssp_Slave samples into a progrom.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;My problem is that:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;When I was debugging using Keil uVision4, the SSP Data Register (SSPx-&amp;gt;DR) was wrote to some wrong values. Take Ssp_Master as an example, when it went in SSP_ReadWrite() -&amp;gt; SSP_SendData(), the value of SSPx-&amp;gt;DR was set to 0x80 or 0xFF, not 0x01~0x3F as I expected. On the other hand, the SSP Status Register SSPx-&amp;gt;SR was always 0x00000003 (meant to Transmit FIFO Empty(TFE) and Transmit FIFO Not Full(TNF)), SSPx-&amp;gt;SR should be written to 0x00000000 or 0x00000002 when the FIFO is full or is sent 1-7 data frame(s), isn't it?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Anyone have already run Ssp_Master/Ssp_Slave sampels on LPC43xx boards, or had similar experience? Share with me please!&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:52:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Is-that-possible-to-build-a-SPI-master-slave-bus-using-SSP0-SSP1/m-p/568653#M17765</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:52:10Z</dc:date>
    </item>
    <item>
      <title>Re: Is that possible to build a SPI master/slave bus using SSP0/SSP1 on one board?</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Is-that-possible-to-build-a-SPI-master-slave-bus-using-SSP0-SSP1/m-p/568654#M17766</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by stanley76726 on Wed Nov 07 05:29:54 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Answering my own question: It is feasible!&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;SPAN&gt;For anyone who are facing similar problems, please view some related discussion on &lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.lpcware.com%2Fshowthread.php%3Ft%3D2803" rel="nofollow" target="_blank"&gt;http://www.lpcware.com/showthread.php?t=2803&lt;/A&gt;&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:52:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Is-that-possible-to-build-a-SPI-master-slave-bus-using-SSP0-SSP1/m-p/568654#M17766</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:52:11Z</dc:date>
    </item>
  </channel>
</rss>

