LPC Microcontrollers中的主题 Re: LPC4330 Ethernet

LPC4330 Ethernet

lpcware — Wed, 15 Jun 2016 18:53:55 GMT

Content originally posted in LPCWare by peufeu on Wed Mar 13 11:56:58 MST 2013
Hello !

Well, I'd just like to give a big thumbs up to the guy(s) who designed the Ethernet system in that chip. I'm testing some very raw bare-metal UDP streaming code I just wrote, and it has no problem saturating the 100Mbps full duplex with 1k UDP packets. In fact it does it with 10-20% cpu load, on the Cortex-M0, with a debug build optimized for size, all the asserts still enabled, and quite small buffers.

I tried to test it with smaller packets (256 bytes) : The M0 interrupts are so fast that it obliterates the quad core PC on the other end of the cable (picture above). The PC really struggles to send more than 20k packets/s. The M0, on the other hand, pushes the packets at almost full wire speed, with more than 50% of the cpu idle. 40.000 packets/s is huge, it never happens on 100 Mbps...

Well, you guys can be proud :D

Re: LPC4330 Ethernet

lpcware — Wed, 15 Jun 2016 18:53:56 GMT

Content originally posted in LPCWare by rgledhill on Mon Apr 08 07:26:21 MST 2013

Hi,

This is a really interesting test! I'd like to mention it in our embedded systems newsletter, if that's ok? Would you mind telling me the clock speed of the M0 core and also the clock speed and OS of the PC, just to rub it in even further? :)

Cheers

Richard

Re: LPC4330 Ethernet

lpcware — Wed, 15 Jun 2016 18:53:57 GMT

Content originally posted in LPCWare by Pacman on Tue Apr 16 21:41:21 MST 2013

Very interesting. I'd be very interested in the following information:

Which PHY are you using ?

-And which mode; are you using RMII or MII ?

If you're using RMII, try and see if you can notch up the speed using MII...

If I understand it correctly, RMII should give a 100Mbits/sec, while MII should give 125Mbits/sec (please correct me if I'm wrong).

Re: LPC4330 Ethernet

lpcware — Wed, 15 Jun 2016 18:53:57 GMT

Content originally posted in LPCWare by lxfriend on Thu Apr 25 06:41:44 MST 2013

Hi all,

I am wondeing if you would like to tell us which OS + diver and stack you are talking about.

I currently have a problem with my FreeRTOS driver for the ethernet chip on the 4350.The driver is working fine in polling mode but I can't use it interupt driven. When the first interrupt comes in it seems I don't get it acknowledged the correct way (the isr is called permanently).

I enabled the Interrupt using CMSIS:

NVIC_SetPrioity(ETHERNET_IRQn,configKERNEL_INTERRUPT_PRIORITY)

NVIC_ClearPendingIRQ(ETHERNET_IRQn)

NVIC_EnableIRQ(ETHERNET_IRQn)

LPC_ETHERNET->DMA_INT_EN = DMA_INT_NOR_SUM | DMA_INT_RECEIVE ;

ISR conent:

uint32_t status = LPC_ETHERNET->DMA_STAT;

LPC_ETHERNET->DMA_STAT= status & 0xFFFF;

--> trigger rx packet processing

Does somebody have an idea whats wrong or is there a sample code availble for the ethernet controller ?

best regards,

Re: LPC4330 Ethernet

lpcware — Wed, 15 Jun 2016 18:53:58 GMT

Content originally posted in LPCWare by jason168 on Mon May 27 03:32:14 MST 2013

NXP LPC43xx谈论群 208457913